W25Q80BL View Datasheet(PDF) - Winbond

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W25Q80BL

2.5V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Winbond 

W25Q80BL

9.1.10 Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI

operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are enabled.

When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are

disabled.

WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during

standard SPI or Dual SPI operation, the QE bit should never be set to a 1.

S7 S6 S5 S4 S3 S2 S1 S0

STATUS REGISTER PROTECT 0

(non-volatile)

SECTOR PROTECT

(non-volatile)

TOP/BOTTOM PROTECT

(non-volatile)

BLOCK PROTECT BITS

(non-volatile)

WRITE ENABLE LATCH

ERASE/WRITE IN PROGRESS

SRP0 SEC TB BP2 BP1 BP0 WEL BUSY

Figure 3a. Status Register-1

S15 S14 S13 S12 S11 S10 S9 S8

SUSPEND STATUS

COMPLEMENT PROTECT

(non-volatile)

SECURITY REGISTER LOCK BITS

(non-volatile OTP)

RESERVED

QUAD ENABLE

(non-volatile)

STATUS REGISTER PROTECT 1

(non-volatile)

SUS CMP LB3 LB2 LB1 (R) QE SRP1

Figure 3b. Status Register-2

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