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W25Q32DWSSIP View Datasheet(PDF) - Winbond

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W25Q32DWSSIP Datasheet PDF : 82 Pages
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W25Q32DW
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2). The
Sector Erase instruction sequence is shown in Figure 21a & 21b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase
instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 3
0
Mode 0
* = MSB
123456789
29 30 31
Instruction (20h)
24-Bit Address
23 22
*
High Impedance
210
Mode 3
Mode 0
Figure 21a. Sector Erase Instruction (SPI Mode)
/CS
CLK
IO0
Mode 3
Mode 0
01234567
Instruction
20h
A23-16
20 16
A15-8
12 8
A7-0
40
Mode 3
Mode 0
IO1
21 17 13 9 5 1
IO2
22 18 14 10 6 2
IO3
23 19 15 11 7 3
Figure 21b. Sector Erase Instruction (QPI Mode)
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Publication Release Date: September 18, 2012
Revision D
 

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