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NB85E View Datasheet(PDF) - NEC => Renesas Technology

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NB85E
NEC
NEC => Renesas Technology NEC
NB85E Datasheet PDF : 226 Pages
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CHAPTER 4 ADDRESS SPACE
4.2 Addressing Mode
The CPU generates two types of addresses: instruction addresses used for instruction fetch and branch
operations; and operand addresses used for data access.
4.2.1 Instruction address
An instruction address is determined by the contents of the program counter (PC), and is automatically
incremented (+2) according to the number of bytes of an instruction to be fetched each time an instruction is executed.
When a branch instruction is executed, the branch destination address is loaded into the PC using one of the following
two addressing modes.
(1) Relative addressing (PC relative)
The signed 9- or 22-bit data of an instruction code (displacement: disp×) is added to the value of the program
counter (PC). At this time, the displacement is treated as 2’s complement data with bits 8 and 21 serving as sign
bits (S).
This addressing is used for the JARL disp22, reg2, JR disp22, and Bcond disp9 instructions.
Figure 4-2. Relative Addressing (1/2)
(a) JARL disp22, reg2 instruction, JR disp22 instruction
31
26 25
0
000000
PC
0
+
31
22 21
0
Sign extension
S
disp22
0
31
26 25
000000
0
PC
0
Memory to be manipulated
User’s Manual U14559EJ3V1UM
39
 

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