UPD161831 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

View to exact match

UPD161831

240/244-OUTPUT TFT-LCD SOURCE DRIVER WITH TIMING GENERATOR (COMPATIBLE WITH 64-GRAY SCALES)

NEC => Renesas Technology 

µPD161831

Figure 4−4. Horizontal Period Amplifier Drive Timing and GCK/GOE1 Signal Output Timing

(When line inversion is set: Laid data input start line to GSTB output line)

µPD161831displaytimingchart <lineinversion, 240outputs, VSYNCwidth=1H, horizontal periodvaliddatainput timing(R1) =16, vertical periodvaliddatainput timing(R2) =2, nodummylind>

Valid data input start line and next line (GSTB output)

Valid data input start line

HSYNC

VSYNC

CLK

56 57 58 59 - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

HCNT

It is a timing chart at the time of using level period effective data input start timing as a 16-dot clock by R1 register.

The address count of a level period starts after level effective data input start timing.

GCLK_O

over 1.0 µs MIN.

GSTB_O

GOE1_O

GOST [5:0]

GOED [5:0]

A setup which does not generate a pulse is prohibited about GOE1 (prohibition of this address

value setup about a start and a stop).

GSTB output

GOE2_O

RSW_O

GSW_O

BSW_O

EXT1_O

EXT2_O

EXT3_O

E1ST [5:0]

E1ED [5:0]

E2ST [5:0]

E2ED [5:0]

E1ST [5:0]

E1ED [5:0]

Y1 to Y240

RST [5:0]

RED [5:0]

GST [5:0]

GED [5:0]

BST [5:0]

BED [5:0]

γ resistance direct driving period

R8 amplifier driving period

Hi-Z

R output

R8 amplifier driving period

γ resistance direct driving period

R8 amplifier driving period

γ resistance direct driving period

G output

B output

Hi-Z

R output

G

COMC

Gn OUT

Gn+1 OUT

24

Preliminary Product Information S16269EJ2V0PM

Share Link: