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UPD17072 View Datasheet(PDF) - NEC => Renesas Technology

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UPD17072 Datasheet PDF : 226 Pages
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µPD17072,17073
Figure 8-2. Configuration of Peripheral Control Registers (1/2)
(BANK1)
Column address
0
1
2
3
4
5
6
7
Row
address
Item
Name
LCD driver Basic timer 0 CE pin status
display
carry register detection
start register
register
Port 1A
Stack pointer
pull-down
resistor select
register
System clock Interrupt edge Interrupt
select register select
enable
register
register
AL
B
CPPPP
SS
S
I BI
III
DC
T
E1111
PP
Y
NTE
PPP
Note
CD
M
AAAA
10
S
TMG
SB
5
OE
0
PPPP
C
1
IT
Symbol 0 0 N N 0 0 0 C 0 0 0
LLLL 00
0 0 0K 0
C
0 OM
Y
DDDD
K
1
3210
Read/
R/W
R&Reset
R
Write
R/W
R/W
R/W
R/W
R/W
Name
Serial I/O Serial I/O
mode select clock select
register
register
IF counter
mode select
register
IF counter
gate status
detection
register
IF counter
control
register
PLL
mode select
register
PLL
PLL
reference
frequency
data register
select register
SSS
SS I I I I
I
II
PP
PPP P PPP
III
I I FFFF
F
FF
LL
LLL L LLL
6
OOO
SH T
OOC CCC
CCMM C C
C
CC
LL
LLL L LLL
G
SR
MM R R R R R R R
Symbol 0 E I S 0 0 K K D D K K 0 0 0
0 0 T E 0 0DD 0 F F F 1 1 1 1
LZ
101010
RS
10
CCC 7 6 5 4
T
KKK
210
Read/
R/W
R/W
R/W
R
Write
W
R/W
R/W
R/W
Note This is a test mode area. Do not write “1” to this area.
48
 

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