UPD16686P View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

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UPD16686P

1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM

NEC => Renesas Technology 

µPD16686, 16687

3.2.2 X address circuit

As shown in Figure 3-6, the display data RAM's X address is specified via the X address register (R3). When using X

address increment mode (INC = 0: control register 2 (R1)), the specified X address is incremented (by 1) each time a

display data read or write operation is executed. The CPU is able to continuously access the display data. The X address is

incremented to 1FH, after which the Y address is incremented after each read or write operation and the X address is set

back to 00H.

For monochrome (black-and-white) display, the X address is incremented to 0FH, after which the Y address is

incremented after each read or write operation and the X address is set back to 00H.

3.2.3 Column address circuit

When displaying the contents of the display data RAM, the column address corresponds to the SEG output, as shown in

Figure 3-6. Similarly, the static icon address corresponds to the PSEG output.

As is shown in Tables 3-1 and 3-2, the correspondence between the display RAM's column address and segment output

can be inverted using the ADC flag in control register 1 (R0) (segment driver direction selection flag). This reduces the

constraints on chip layout when assembling the LCD module.



Table 3-1. Relationship Between Column Address and SEG Output

SEG Output

ADC

0

(D1)

1

SEG1

00H

→

7FH

←

Column address

Column address

SEG128

→

7FH

←

00H



Table 3-2. Relationship Between Column Address for Static Icon and PSEG Output

PSEG Output

ADC

0

(D1)

1

PSEG1

00H

→

04H

←

Column address

Column address

PSEG20

→

04H

←

00H

3.2.4 Y address circuit

As is shown in Figure 3-6, the Y address register (R4) is used to specify the display data RAM's Y address. When using

Y address increment mode (INC = 1: control register 2 (R1)), the specified Y address is incremented (by 1) each time a

display data read or write operation is executed. The CPU is able to continuously access the display data. The Y address

is incremented to 7FH, after which the X address is incremented after each read or write operation and the Y address is set

back to 00H.

3.2.5 Common scan circuit

The common scan circuit sets the scan lines for common signals. The scan direction is set using the COMR flag in control

register 1 (R0), as shown in Table 3-3.

For example, when using 1/80 duty, when COMR = L the scan direction is COM1 → COM80 and when COMR = H,

the scan direction is COM80 → COM1 using the COM80 to COM1 pins.



Table 3-3. Relationship Between Common Scan Circuit and Scan Direction

COMR

0

COM1

→

COM128

(D0)

1

COM128

←

COM1

26

Data Sheet S15548EJ1V0DS

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