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54LS377 View Datasheet(PDF) - Motorola => Freescale

Part Name
Description
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54LS377 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
SN54/74LS377 SN54/74LS378 SN54/74LS379
GUARANTEED OPERATING RANGES
Symbol
VCC
Supply Voltage
Parameter
Min
Typ
Max
Unit
54
4.5
5.0
5.5
V
74
4.75
5.0
5.25
TA
Operating Ambient Temperature Range
54
– 55
25
125
°C
74
0
25
70
IOH
Output Current — High
IOL
Output Current — Low
54, 74
54
74
– 0.4
mA
4.0
mA
8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
VIH
Parameter
Input HIGH Voltage
Limits
Min Typ Max Unit
Test Conditions
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
VIK
VOH
54
Input LOW Voltage
74
0.7
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
Input Clamp Diode Voltage
– 0.65 – 1.5
V
VCC = MIN, IIN = – 18 mA
Output HIGH Voltage
54
2.5
3.5
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
V
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
V
IOL = 8.0 mA
per Truth Table
IIH
Input HIGH Current
IIL
Input LOW Current
IOS
Short Circuit Current (Note 1)
– 20
LS377
ICC
Power Supply Current LS378
LS379
20
µA VCC = MAX, VIN = 2.7 V
0.1
mA VCC = MAX, VIN = 7.0 V
– 0.4 mA VCC = MAX, VIN = 0.4 V
– 100 mA VCC = MAX
28
22
mA VCC = MAX, NOTE 1
15
NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock.
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay,
Clock to Output
30
40
MHz
17
18
27
27
ns
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
tW
Any Pulse Width
20
ns
ts
Data Setup Time
20
ns
ts
Enable Setup
Inactive — State
10
Time
Active — State
25
ns
ns
th
Any Hold Time
5.0
ns
Test Conditions
VCC = 5.0 V
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
FAST AND LS TTL DATA
5-536
 

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