UBA2033TS View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

View to exact match

UBA2033TS

HF full bridge driver IC

NXP Semiconductors. 

NXP Semiconductors

HF full bridge driver IC

Product specification

UBA2033

FUNCTIONAL DESCRIPTION

Supply voltage

The UBA2033 is powered by a supply voltage applied to

pin HV, for instance the supply voltage of the full bridge.

The IC generates its own low supply voltage for the

internal circuitry. Therefore an additional low voltage

supply is not required. A capacitor has to be connected to

pin VDD to obtain a ripple-free internal supply voltage.

The circuit can also be powered by a low voltage supply

directly applied to pin VDD. In this case pin HV should be

connected to pin VDD or SGND.

Start-up

With an increasing supply voltage the IC enters the

start-up state; the higher power transistors are kept off and

the lower power transistors are switched on. During the

start-up state the bootstrap capacitors are charged and the

bridge output current is zero. The start-up state is defined

until VDD = VDD(UVLO), where UVLO stands for Under

Voltage Lock-out. The state of the outputs during the

start-up phase is overruled by the bridge disable function.

Release of the power drive

At the moment the supply voltage on pin VDD or HV

exceeds the level of release power drive, the output

voltage of the bridge depends on the control signal on

pin EXTDR (see Table 1). The bridge position after

start-up, disable, or delayed start-up (via pin SU) depends

on the status of the pins DD and EXTDR. If pin DD = LOW

(divider enabled) the bridge will start in the pre-defined

position: pin GLR and pin GHL = HIGH and pin GLL and

pin GHR = LOW. If pin DD = HIGH (divider disabled) the

bridge position will depend on the status of pin EXTDR.

If the supply voltage on pin VDD or HV decreases and

drops below the reset level of power drive the IC enters the

start-up state again.

Oscillation

At the point where the supply voltage on pin HV crosses

the level of release power drive, the bridge begins

commutating between the following two defined states:

• Higher left and lower right MOSFETs on,

higher right and lower left MOSFETs off

• Higher left and lower right MOSFETs off,

higher right and lower left MOSFETs on.

The oscillation can take place in three different modes:

• Internal oscillator mode.

In this mode the bridge commutating frequency is

determined by the values of an external resistor (Rosc)

and capacitor (Cosc). In this mode pin EXTDR must be

connected to pin +LVS. To realize an accurate 50% duty

factor, the internal divider should be used. The internal

divider is enabled by connecting pin DD to SGND. Due

to the presence of the divider the bridge frequency

is half the oscillator frequency. The commutation of the

bridge will take place at the falling edge of the signal on

pin RC. To minimize the current consumption

pins +LVS, −LVS and EXTDR can be connected

together to either pin SGND or VDD. In this way the

current source in the logic voltage supply circuit is shut

off.

• External oscillator mode without the internal divider.

In the external oscillator mode the external source is

connected to pin EXTDR and pin RC is short-circuited to

pin SGND to disable the internal oscillator. If the internal

divider is disabled (pin DD = VDD) the duty factor of the

bridge output signal is determined by the external

oscillator signal and the bridge frequency equals the

external oscillator frequency.

• External oscillator mode with the internal divider.

The external oscillator mode can also be used with the

internal divider function enabled (pin RC and

pin DD = SGND). Due to the presence of the divider the

bridge frequency is half the external oscillator

frequency. The commutation of the bridge is triggered by

the falling edge of the EXTDR signal with respect to

V−LVS.

The design equation for the bridge oscillator frequency is:

fbridge

=

------------------------1--------------------------

(kosc × Rosc × Cosc)

Non-overlap time

The non-overlap time is the time between turning off the

conducting pair of MOSFETs and turning on the next pair.

The non-overlap time is internally fixed to a very small

value, which allows an HID system to operate with a very

small phase difference between load current and full

bridge voltage (pins SHL and SHR). Especially when

igniting an HID lamp via a LC resonance circuit, a small

‘dead time’ is essential. The high maximum operating

frequency, together with a small ‘dead time’, also gives the

opportunity to ignite the HID lamp at the third harmonic of

the full bridge voltage, thereby reducing costs in the

magnetic power components.

2002 Oct 08

5

Share Link: