UAA3535 View Datasheet(PDF) - Philips Electronics

Part Name

Description

View to exact match

UAA3535

Fully integrated DECT transceiver

Philips Electronics 

Philips Semiconductors

Low power GSM/DCS/PCS multi-band transceiver

Objective specification

UAA3535HL

IF DIVIDER CONTROL

The IF divider can be programmed to divide the integrated

IF VCO frequency by 1 or 2. The selection of these

2 modes is accomplished by the control bit IFDIV;

see Table 8.

Table 8 IF divider control

BIT IFDIV

0

1

IF DIVIDER MODE

IF = fVCO

IF = fVCO divided by 2

TXIF FILTER CONTROL

The transmit section integrates two switchable low-pass

filters, one for a 45.5 MHz IF and the other one for

91 MHz IF. The selection of these 2 modes is

accomplished by the control bit FILT; see Table 9.

Table 9 TXIF filter control

BIT FILT

0

1

TXIF FILTER MODE

IF 45.5 MHz

IF 91 MHz

IF SYNTHESIZER DIVIDER CONTROL

The IF synthesizer divider can be programmed to divide

the semi-integrated IF VCO frequency by 6 or 7.

The selection of these 2 modes is accomplished by the

control bit IFO; see Table 10.

Table 10 IF synthesizer divider control

BIT IFO

0

1

IF SYNTHESIZER

DIVIDER MODE

divide-by-6

divide-by-7

Programming

SERIAL PROGRAMMING BUS

A simple 3-wire unidirectional serial bus is used to program

the circuit. The 3 lines are DATA, CLK and E (enable).

The data sent to the device is loaded in bursts framed

by E. Programming clock edges are ignored until E goes

active LOW. The programmed information is loaded into

the addressed latch when E returns inactive HIGH. This is

allowed when CLK is in either state without causing any

consequences to the register data. Only the last 17 bits

serially clocked into the device are retained within the

programming register. Additional leading bits are ignored,

and no check is made on the number of clock pulses.

The fully static CMOS design uses virtually no current

when the bus is inactive. It can always capture new

programming data even during power-down of both

synthesizers.

DATA FORMAT

Data is entered with the most significant bit first.

The leading bits make up the data field, while the trailing

4 bits are an address field. The address bits are decoded

on the rising edge of E. This produces an internal load

pulse to store the data in the addressed latch. To ensure

that data is correctly loaded on first power-up, E should be

held LOW and only taken High after having programmed

an appropriate register. To avoid erroneous divider ratios,

the pulse is inhibited during the period when data is read

by the frequency dividers. This condition is guaranteed by

respecting a minimum E pulse width after data transfer.

The allocation of the register bits is given in Table 11.

REGISTER PRESET CONDITIONS

The UAA3535HL programming registers have a preset

state. The preset values can be found in Table 12.

Conditions for guaranteed preset values at power-on are

as follows:

• DATA, CLOCK, E, SYNON, RXON and TXON must be

at 0 V

• Preset value is guaranteed 2 ms after VCC(SYN) rises

to 90% of 2.6 V

• E should stay at 0 V up to the end of the first

programming word.

2000 Feb 17

8

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