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UAA3220TS View Datasheet(PDF) - Philips Electronics

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UAA3220TS Datasheet PDF : 32 Pages
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Philips Semiconductors
Frequency Shift Keying (FSK)/Amplitude
Shift Keying (ASK) receiver
Product specification
UAA3220TS
Data slicer
Data detection is provided by means of a level comparator
with adaptive slice reference. After the first data filter stage
the pre-filtered data is split into two paths. One passes the
second data filter stage and is fed to the positive
comparator input. The other path is fed to an integration
circuit with a large time constant in order to derive the
average value (DC component) as an adaptive slice
reference which is presented to the negative comparator
input. The internal buffer provides 13 dB AC voltage gain.
The adaptive reference allows to detect the received data
over a large range of noise floor levels. The integration
circuit consists of a simple RC low-pass filter with on-chip
resistors. The data slicer output is designed with internal
pull-up.
RSSI buffer
The RSSI buffer is an amplifier with a voltage gain of 0 dB.
At FSK receive mode the RSSI output provides a field
strength indication. It has an output impedance of 10 k.
Figure 3 shows the level curve (RSSI curve) as a function
of the limiter input voltage (RMS value).
1.55
handbook, full pagewidth
VRSSI
(V)
1.45
1.35
1.25
MGM744
(1)
(2)
(3)
1.15
10-7
(1) Tamb = 85 °C.
(2) Tamb = 27 °C.
(3) Tamb = 40 °C.
10-6
10-5
10-4
10-3
Fig.3 Level curve VRSSI as a function of VLIN(rms).
10-2 VLIN(rms) (V) 10-1
1999 Jan 22
6
 

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