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RB5C396 View Datasheet(PDF) - RICOH Co.,Ltd.

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Description
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RB5C396 Datasheet PDF : 93 Pages
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RF5C296/RF5C396L/RB5C396/RF5C396
bit4 to bit0 : Power Control Bits. These bits cooperate with bit0 in the Mode Control Register (Index : 2Fh) to set the
VCC3EN, VCC5EN, VPP_EN1, and VPP_EN0 pin signals to “0” or “1” as shown in the table below :
bit4 bit3*1 bit2*1 bit1
1´´0
1´´0
1´´0
1´´0
1´´1
1´´1
1´´1
1´´1
0´´´
bit0
bit0 of Mode
Control Register
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
´
´
VCC3EN#
1
0
1
0
1
0
1
0
1
VCC5EN#
01
0
01
0
01
0
01
0
1
VPP_EN1*2
0
0
0
0
1
1
1
1
1
VPP_EN0*3
0
0
1
1
0
0
1
1
0
*1) bit3 and bit2 : don't care. VCCnEN# means VCC5EN# or VCC3EN#, this signal defined by voltage selection.
*2) The settings of bits 3 and 2 are don't care. The settings of the VPP_EN1 and VPP_EN0 pin signals to “0” and “0”, “0” and “1”, “1” and “0”, and “1” and
“1” specify their connection to no pin, connection to the VCC pin, connection to the VPP pin, and reservation, respectively.
1.4 Card Status Change Register
Index : 04h
Default value : 0000 0000h Read & Write
bit7tobit5 : Reserved
bit4
: GPI Change Bit. This bit will be set upon generation of any interrupt due to the GPI pin status change.
This bit is held at “0” unless the GPI Enable Bit is set to “1” in the Card Detect and General Control
Register.
bit3
: Card Detect Change. Bit is set to “1” when a change has been detected on either the CD#1 or CD2# pin.
bit2
: Ready Change. Bit is set to “1” when a low to high has been detected on the Ready/Busy# pin. Bit reads
“0” for I/O cards.
bit1
: Bit is set to “1” when Battery Warning Condition has been detected. For the Battery Warning Condition,
see the description of bits1 and 0 in the Interface Status Register (Index : 01h). Bit reads “0” for I/O
cards.
bit0
: Bit is set to “1” when Battery Dead Condition has been detected for memory card. For the Battery
Warning Condition, see the description of bits1 and 0 in the Interface Status Register (Index : 01h).
For I/O cards, bit is set to “1” if Ring Indicate Enable bit in the Interrupt and General Control Register is
set to “0” and STSCHG#/RI# signal from I/O card has been pulled low. This bit reads “0” for I/O cards
if the Ring Indicate Enable bit in the Interrupt and General Control Register is set to “1”.
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