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TS68040MFT1D/T35A View Datasheet(PDF) - Atmel Corporation

Part Name
Description
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TS68040MFT1D/T35A
Atmel
Atmel Corporation Atmel
TS68040MFT1D/T35A Datasheet PDF : 49 Pages
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Table 3. Signal Index (Continued)
Signal Name
Mnemonic
Bus Clock
BCLK
Processor Clock
PCLK
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Test Reset
Power Supply
Ground
TCK
TMS
TDI
TDO
TRST
VCC
GND
Function
Clock input used to derive all bus signal timing
Clock input used for internal logic timing. The PCLK frequency is exactly 2X the
BCLK frequency
Clock signal for the IEEE P1149.1 test access port (TAP)
Selects the principle operations of the test-support circuitry
Serial data input for the TAP
Serial data output for the TAP
Provides an asynchronous reset of the TAP controller
Power supply
Ground connection
Scope
This drawing describes the specific requirements for the microprocessor TS68040 -
25 MHz and 33 MHz, in compliance with MIL-STD-883 class B or Atmel standard
screening.
Applicable
Documents
MIL-STD-883
1. MIL-STD-883: test methods and procedures for electronics.
2. MIL-I-38535: general specifications for microcircuits.
3. DESC 5962-93143.
Requirements
General
The microcircuits are in accordance with the applicable document and as specified
herein.
Design and Construction
Terminal Connections
See Figure 2 and Figure 3.
Lead Material and Finish
Lead material and finish shall be as specified in MIL-STD-883 (see enclosed “MIL-STD-
883 C and Internal Standard” on page 46).
Package
The macro circuits are packaged in hermetically sealed ceramic packages which con-
form to case outlines of MIL-STD-1835-or as follow:
• CMGA 10-179-PAK pin grid array, but see “179 pins – PGA” on page 43.
• Similar to CQCC1-F196C-U6 ceramic uniform lead chip carrier package with
ceramic nonconductive tie-bar but use Atmel’s internal drawing, see “196 pins – Tie
Bar CQFP Cavity Up (on request)” on page 44.
• Gullwing shape CQFP see “196 pins – Gullwing CQFP cavity up” on page 45.
8 TS68040
2116A–HIREL–09/02
 

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