|TS68040VFT1U35A||Third-Generation 32-bit Microprocessor|
|TS68040VFT1U35A Datasheet PDF : 49 Pages |
A global bit can be set in each page descriptor to prevent flushing of the ATC entry for
that page by some PFLUSH instruction variants, allowing system ATC entries to remain
resident during task swaps. If these special PFLUSH instructions are not used, this bit
can be user defined. The MMUs automatically maintain access history information for
the pages by updating the used (U) and modified (M) status bits.
The MMU instructions supported by the TS68040 are as follows:
PFLUSH: Allows flushing of either selected ATC entries by function code and logical
address or the entire ATCs.
PTEST: Takes an address and function code and searches the translation tables for the
corresponding entry, which is then loaded into the ATC. The results of the search are
available in the MMU status register and are often useful in determining the cause of a
All of the TS68040 MMU instructions are privileged and can only be executed from the
Four transparent translation registers, two each for instruction and data accesses, have
been provided on the TS68040 MMU to allow portions of the logical address space to be
transparently mapped and accessed without the need for corresponding entries resident
in the ATC. Each register can be used to define a range of logical addresses from
16M bytes to 4G bytes with a base address and a mask. All addresses within these
ranges are not mapped, and are optionally protected against user or supervisor
accesses and write accesses. Logical addresses in these areas become the physical
addresses for memory access. The transparent translation feature allows rapid move-
ment of large blocks of data in memory or I/O space without disturbing the context of the
on-chip ATCs or incurring delays associated with translation table searches.
Microcircuits are prepared for delivery in accordance with MIL-M-38510 or Atmel
Certificate of Compliance Atmel offers a certificate of compliances with each shipment of parts, affirming the prod-
ucts are in compliance either with MIL-STD-883 or Atmel standard and guarantying the
parameters not tested at temperature extremes for the entire temperature range.
MOS devices must be handled with certain precautions to avoid damage due to accu-
mulation of static charge. Input protection devices have been designed in the chip to
minimize the effect of this static buildup. However, the following handling practices are
a) Devices should be handled on benches with conductive and grounded surfaces.
b) Ground test equipment, tools and operator.
c) Do not handle devices by the leads.
d) Store devices in conductive foam or carriers.
e) Avoid use of plastic, rubber, or silk in MOS areas.
f) Maintain relative humidity above 50 percent if practical.
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