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TS68040VFT1U35A View Datasheet(PDF) - Atmel Corporation

Part NameDescriptionManufacturer
TS68040VFT1U35A Third-Generation 32-bit Microprocessor Atmel
Atmel Corporation Atmel
TS68040VFT1U35A Datasheet PDF : 49 Pages
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Address Translation Cache
Translation Tables
An integral part of the translation function previously described is the dual cache mem-
ory that stores recently used logical-to-physical address translation information (page
descriptors) for instruction and date accesses. These caches are 64-entry, four-way, set
associative. Each ATC compare the logical address of the incoming access against its
entries. If one of the entries matches, there is a hit, and the ATC sends the physical
address to the bus controller, which then starts the external bus cycle (provided there
was no hit in the corresponding cache for the access).
The translation tables of the TS68040 have a three level tree structure and reside in
main memory. Since only a portion of the complete tree needs to exist at any one time,
the tree structure minimizes the amount of memory necessary to set up the tables for
most programs. As shown in Figure 20, either the user root pointer or the supervisor root
pointer points to the first level table, depending on the values of the function code for an
access. Table entries at the second level of the tree (pointer tables) contain pointers to
the third level (page tables). Entries in the page tables contain either page descriptors or
indirect pointers to page descriptors. The mechanism for performing table search opera-
tions uses portions of the logical address (as indices) at each level of the search. All
addresses in the translation table entries are physical addresses.
Figure 22. Translation Table Structure
There are two variations of table searches for both 4K and 8K page sizes: normal
searches and indirect searches. An indirect search differs in that the entry in the third
level page table contains a pointer to a page descriptor rather than the page descriptor
Entries in the translation tables contain control and status information on addition to the
physical address information. Control bits specify write protection, limit access to super-
visor only, and determine cachability of data in each memory page. Each page
descriptor also has two user-programmable bits that appear on the UPA0 and UPA1 sig-
nals during an external access for use as address modifier bits.
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