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TS68040MFU25A View Datasheet(PDF) - Atmel Corporation

Part NameTS68040MFU25A Atmel
Atmel Corporation Atmel
DescriptionThird-Generation 32-bit Microprocessor
TS68040MFU25A Datasheet PDF : 49 Pages
First Prev 41 42 43 44 45 46 47 48 49
Address Translation Cache
Translation Tables
An integral part of the translation function previously described is the dual cache mem-
ory that stores recently used logical-to-physical address translation information (page
descriptors) for instruction and date accesses. These caches are 64-entry, four-way, set
associative. Each ATC compare the logical address of the incoming access against its
entries. If one of the entries matches, there is a hit, and the ATC sends the physical
address to the bus controller, which then starts the external bus cycle (provided there
was no hit in the corresponding cache for the access).
The translation tables of the TS68040 have a three level tree structure and reside in
main memory. Since only a portion of the complete tree needs to exist at any one time,
the tree structure minimizes the amount of memory necessary to set up the tables for
most programs. As shown in Figure 20, either the user root pointer or the supervisor root
pointer points to the first level table, depending on the values of the function code for an
access. Table entries at the second level of the tree (pointer tables) contain pointers to
the third level (page tables). Entries in the page tables contain either page descriptors or
indirect pointers to page descriptors. The mechanism for performing table search opera-
tions uses portions of the logical address (as indices) at each level of the search. All
addresses in the translation table entries are physical addresses.
Figure 22. Translation Table Structure
There are two variations of table searches for both 4K and 8K page sizes: normal
searches and indirect searches. An indirect search differs in that the entry in the third
level page table contains a pointer to a page descriptor rather than the page descriptor
Entries in the translation tables contain control and status information on addition to the
physical address information. Control bits specify write protection, limit access to super-
visor only, and determine cachability of data in each memory page. Each page
descriptor also has two user-programmable bits that appear on the UPA0 and UPA1 sig-
nals during an external access for use as address modifier bits.
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The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device.

• 26-42 MIPS Integer Performance
• 3.5-5.6 MFLOPS Floating-Point-Performance
• IEEE 754-Compatible FPU
• Independent Instruction and Data MMUs
• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously
• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
• Multimaster/Multiprocessor Support via Bus Snooping
• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput
• 4G bytes Direct Addressing Range
• Software Support Including Optimizing C Compiler and UNIX® System V Port
• IEEE P 1149-1 Test Mode (JTAG)
• f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W
• The Use of the TS88915T Clock Driver is Suggested


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