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TS68040VF1D/T35A View Datasheet(PDF) - Atmel Corporation

Part NameDescriptionManufacturer
TS68040VF1D/T35A Third-Generation 32-bit Microprocessor Atmel
Atmel Corporation Atmel
TS68040VF1D/T35A Datasheet PDF : 49 Pages
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Exception Processing
Memory Management
Translation Mechanism
The TS68040 provides the same extensions to the exception stacking process as the
TS68030. If the M bit in the status register is set, the master stack pointer is used for all
task-related exceptions. When a nontask-related exception occurs (i.e., an interrupt),
the M bit is cleared, and the interrupt stack pointer is used. This feature allows a task’s
stack area to be carried within a single processor control block, and new tasks may be
initiated by simply reloading the master stack pointer and setting the M bit.
The externally generated exceptions are interrupts, bus errors, and reset conditions.
The interrupts are requests from external devices for processor action; whereas, the bus
error and reset signals are used for access control and processor initialization. The
internally generated exceptions come from instructions, address errors, tracing, or
breakpoints. The TRAP, TRAPcc, TRAPVcc, FTRAPcc, CHK, CHK2, and DIV instruc-
tions can all generate exceptions as part of their instruction execution. Tracing behaves
like a very high-priority, internally generated interrupt whenever it is processed. The
other internally generated exceptions are caused by unimplemented floating-point
instructions, illegal instructions, instruction fetches from odd addresses, and privilege
violations. Finally, the MMU can generate exceptions, for access violations and for when
invalid descriptors are encountered during table searches.
Exception processing for the TS68040 occurs on the following sequence:
1. an internal copy is made of the status register,
2. the vector number of the exception is determined,
3. current processor status is saved,
4. the exception vector offset is determined by multiplying the vector number by
This offset is then added to the contents of the VBR to determine the memory address
of the exception vector. The instruction at the address given in the exception vector is
fetched, and normal instruction decoding and execution is started.
The full addressing range of the TS68040 is 4G bytes (4,294,967,296 bytes). However,
most TS68040 systems implement a much smaller physical memory. Nonetheless, by
using virtual memory techniques, the system can be made to appear to have a full
4G bytes of physical memory available to each user program. The independent instruc-
tion and data MMUs fully support demand paged virtual-memory operating systems with
either 4K or 8K page sizes. In addition to its main function of memory management,
each MMU protects supervisor areas from accesses by user programs and also pro-
vides write protection on a page-by-page basis. For maximum efficiency, each MMU
operates in parallel with other processor activities.
Because logical-to-physical address translation is one of the most frequently executed
operations of the TS68040 MMUs, this task has been optimized. Each MMU initiates
address translation by searching for a descriptor containing the address translation
information in the ATC. If the descriptor does not reside in the ATC, then the MMU per-
forms external bus cycles via the bus controller to search the translation tables in
physical memory. After being located, the page descriptor is loaded into the ATC, and
the address is correctly translated for the access, provided no exception conditions are
40 TS68040
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