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TS68040MFD/T35A View Datasheet(PDF) - Atmel Corporation

Part NameDescriptionManufacturer
TS68040MFD/T35A Third-Generation 32-bit Microprocessor Atmel
Atmel Corporation Atmel
TS68040MFD/T35A Datasheet PDF : 49 Pages
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Introduction
TS68040
The TS68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the inte-
ger unit processing capabilities of the TS68030 microprocessor with independent
4K bytes data and instruction caches and an on-chip FPU. The TS68040 maintains the
32-bit registers available with the entire TS68000 Family as well as the 32-bit address
and data paths, rich instruction set, and versatile addressing modes. Instruction execu-
tion proceeds in parallel with accesses to the internal caches, MMU operations, and bus
controller activity. Additionally, the integer unit is optimized for high-level language
environments.
The TS68040 FPU is user-object-code compatible with the TS68882 floating-point
coprocessor and conforms to the ANSI/IEEE Standard 754 for binary floating-point arith-
metic. The FPU has been optimized to execute the most commonly used subset of the
TS68882 instruction set, and includes additional instruction formats for single and dou-
ble-precision rounding of results. Floating-point instructions in the FPU execute
concurrently with integer instructions in the integer unit.
The MMUs support multiprocessing, virtual memory systems by translating logical
addresses to physical addresses using translation tables stored in memory. The MMUs
store recently used address mappings in two separate ATCs-on-chip. When an ATC
contains the physical address for a bus cycle requested by the processor, a translation
table search is avoided and the physical address is supplied immediately, incurring no
delay for address translation. Each MMU has two transparent translation registers avail-
able that define a one-to-one mapping for address space segments ranging in size from
16M bytes to 4G bytes each.
Each MMU provides read-only and supervisor-only protections on a page basis. Also,
processes can be given isolated address spaces by assigning each a unique table
structure and updating the root pointer upon a task swap. Isolated address spaces pro-
tect the integrity of independent processes.
The instruction and data caches operate independently from the rest of the machine,
storing information for fast access by the execution units. Each cache resides on its own
internal address bus and internal data bus, allowing simultaneous access to both. The
data cache provides write through or copyback write modes that can be configured on a
page-by-page basis.
The TS68040 bus controller supports a high-speed, non multiplexed, synchronous
external bus interface, which allows the following transfer sizes: byte, word (2 bytes),
long word (4 bytes), and line (16 bytes). Line accesses are performed using burst trans-
fers for both reads and writes to provide high data transfer rates.
3
2116A–HIREL–09/02
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