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TS68040MFU25A View Datasheet(PDF) - Atmel Corporation

Part NameTS68040MFU25A Atmel
Atmel Corporation Atmel
DescriptionThird-Generation 32-bit Microprocessor
TS68040MFU25A Datasheet PDF : 49 Pages
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TS68040
Cache Coherency
Cache Instructions
Operand Transfer
Mechanisms
Transfer Types
Burst Transfer Operation
Bus Snooping
2116A–HIREL–09/02
Cachability of data in each memory page is controlled by two bits in the page descriptor
for each page. Cachable pages may be either write through or copyback, with no write-
allocate for misses to write through pages. Non-cachable pages may also be specified
as non-cachable I/O, forcing accesses to these pages to occur in order of instruction
execution.
The TS68040 has the ability to snoop the external bus during accesses by other bus
masters to maintain coherency between the TS68040’s caches and external memory
systems. External write cycles are snooped by both the instruction cache and data
cache; whereas, external read cycles are snooped only by the data cache. In addition,
external cycles can be flagged on the bus as snoopable or non snoopable. When an
external cycle is marked as snoopable, the bus snooper checks the caches for a coher-
ency conflict based on the state of the corresponding cache line and the type of external
cycle.
Although the internal execution units and the bus snooper circuit all have access to the
on-chip caches, the snooper has priority over the execution units to allow the snooper to
resolve coherency discrepancies immediately.
The TS68040 supports the following instructions for cache maintenance. Both instruc-
tions may selectively operate on the data or instruction cache.
CINV: Invalidates a single line, all lines in a physical page, or the entire cache.
CPUSH: Pushes selected dirty data cache lines to memory, then invalidates all selected
lines.
The TS68040 external synchronous bus supports multiple masters and overlaps arbitra-
tion with data transfers. The bus is optimized to perform high-speed transfers to and
from an external cache or memory. The data and address buses are each 32 bits wide.
The TS68040 provides two signals (TT1-TT0) that define four types of bus transfers:
normal access, MOVE16 access, alternate access, and interrupt acknowledge access.
Normal accesses identify normal memory references: MOVE16 accesses are memory
accesses by a MOVE16 instruction; and alternate accesses identify accesses to the
undefined address spaces (function code values of 0, 3, 4, 7). The interrupt acknowl-
edge access is used to fetch an interrupt vector during interrupt exception processing.
During burst read write to cache transfers, the values on the address and transfer type
signals do not change; they are the address of the first requested item of the cache line.
When the TS68040 request a burst read transfer of a cache line, the address bus indi-
cates the address of the long word in the line needed first, but the memory system is
expected to provide data in the following order (modulo 4): 0, 1, 2, 3 (long-word offsets).
The first address needed may not be from offset 0; nevertheless, all four long words
must be transferred. Burst writes occur in a similar manner.
Bus snooping ensures that data in main memory is consistent with data in the on-chip
caches. If an alternate bus master is performing a read transfer on the bus and snooping
is enabled, and if the snoop logic determines that the on-chip data cache has dirty data
(data valid but not consistent with memory) for this transfer, the memory is prevented
from responding to the read request, and the TS68040 supplies the data directly to the
master. If the alternate master is performing a write transfer on the bus and snooping is
enabled, and if the snooper determines that one of the on-chip caches has a valid line
for this request, then the snooper may either invalidate or update the line as selected by
the snoop control signals.
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Description
The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device.

Features
• 26-42 MIPS Integer Performance
• 3.5-5.6 MFLOPS Floating-Point-Performance
• IEEE 754-Compatible FPU
• Independent Instruction and Data MMUs
• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously
• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
• Multimaster/Multiprocessor Support via Bus Snooping
• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput
• 4G bytes Direct Addressing Range
• Software Support Including Optimizing C Compiler and UNIX® System V Port
• IEEE P 1149-1 Test Mode (JTAG)
• f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W
• The Use of the TS88915T Clock Driver is Suggested

 

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