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TS68040DESC01YCA View Datasheet(PDF) - Atmel Corporation

Part NameTS68040DESC01YCA Atmel
Atmel Corporation Atmel
DescriptionThird-Generation 32-bit Microprocessor
TS68040DESC01YCA Datasheet PDF : 49 Pages
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Figure 21. Cache Organization Overview
The caches are accessed by physical addresses from the on-chip MMUs. The transla-
tion of the upper bits of the logical address occurs concurrently with the accesses into
the set array in the cache by the lower address bits. The output of the ATC is compared
with the tag field in the cache to determine if one of the lines in the selected set matches
the translated physical address. If the tag matches and the entry is valid, then the cache
has a hit.
If the cache hits and the access is a read, the appropriate long word from the cache line
is multiplexed onto the appropriate internal bus. If the cache hits and the access is a
write, the data, regardless of size, is written to the appropriate portion of the correspond-
ing longword entry in the cache.
When a data cache miss occurs and a previously valid cache line is needed to cache
the new line, any dirty data in the old line will be internally buffered and copied back to
memory after the new cache line has been loaded.
Pushing of dirty data can be forced by the CPUSH instruction.
38 TS68040
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The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device.

• 26-42 MIPS Integer Performance
• 3.5-5.6 MFLOPS Floating-Point-Performance
• IEEE 754-Compatible FPU
• Independent Instruction and Data MMUs
• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously
• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
• Multimaster/Multiprocessor Support via Bus Snooping
• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput
• 4G bytes Direct Addressing Range
• Software Support Including Optimizing C Compiler and UNIX® System V Port
• IEEE P 1149-1 Test Mode (JTAG)
• f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W
• The Use of the TS88915T Clock Driver is Suggested


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