Figure 21. Cache Organization Overview
The caches are accessed by physical addresses from the on-chip MMUs. The transla-
tion of the upper bits of the logical address occurs concurrently with the accesses into
the set array in the cache by the lower address bits. The output of the ATC is compared
with the tag field in the cache to determine if one of the lines in the selected set matches
the translated physical address. If the tag matches and the entry is valid, then the cache
has a hit.
If the cache hits and the access is a read, the appropriate long word from the cache line
is multiplexed onto the appropriate internal bus. If the cache hits and the access is a
write, the data, regardless of size, is written to the appropriate portion of the correspond-
ing longword entry in the cache.
When a data cache miss occurs and a previously valid cache line is needed to cache
the new line, any dirty data in the old line will be internally buffered and copied back to
memory after the new cache line has been loaded.
Pushing of dirty data can be forced by the CPUSH instruction.