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TS68040VFT1U35A View Datasheet(PDF) - Atmel Corporation

Part NameTS68040VFT1U35A Atmel
Atmel Corporation Atmel
DescriptionThird-Generation 32-bit Microprocessor
TS68040VFT1U35A Datasheet PDF : 49 Pages
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Table 20. Instruction Set Summary (Continued)
Mnemonic
Description
ILLEGAL
Take Illegal Instruction Trap
JMP
JSR
Jump
Jump To Subroutine
LEA
LINK
LSL, LSR
Load Effective Address
Link And Allocate
Logical Shift Left And Right
MOVE
MOVE16(1)
MOVEA
MOVE CCR
MOVE SR
MOVE USP
MOVEC(1)
MOVEM
MOVEP
MOVEQ
MOVES(1)
MULS
MULU
Move
16-byte Block Move
Move Address
Move Condition Code Register
Move Status Register
Move User Stack Pointer
Move Control Register
Move Peripheral
Move Quick
Move Alternate Address Space
Move Multiply
Signed Multiply
Unsigned Multiply
NBCD
NEG
NEGX
NOP
NOT
Negate decimal with extend
Negate
Negate with extend
No operation
Logical complement
OR
Logical Inclusive OR
ORI
Logical Inclusive OR Immediate
PACK
PEA
PFLUSH(1)
PTEST(1)
Pack BCD
Push Effective Address
Flush Entry(ies) In The ATCs
Test A Logical Address
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
Reset External Devices
Rotate Left And Right
Rotate With Extend Left And Right
Return And Deallocate
Return From Exception
Return And Restore Codes
Return From Subroutine
TS68040
35
2116A–HIREL–09/02
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Description
The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device.

Features
• 26-42 MIPS Integer Performance
• 3.5-5.6 MFLOPS Floating-Point-Performance
• IEEE 754-Compatible FPU
• Independent Instruction and Data MMUs
• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously
• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
• Multimaster/Multiprocessor Support via Bus Snooping
• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput
• 4G bytes Direct Addressing Range
• Software Support Including Optimizing C Compiler and UNIX® System V Port
• IEEE P 1149-1 Test Mode (JTAG)
• f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W
• The Use of the TS88915T Clock Driver is Suggested

 

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