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TS68040MFU25A View Datasheet(PDF) - Atmel Corporation

Part NameTS68040MFU25A Atmel
Atmel Corporation Atmel
DescriptionThird-Generation 32-bit Microprocessor


TS68040MFU25A Datasheet PDF : 49 Pages
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34 TS68040
The instruction provided by the TS68040 are listed in Table 20. The instruction set has
been tailored to support high-level languages and is optimized for those instructions
most commonly executed (however, all instructions listed are fully supported). Many
instructions operate on bytes, words, and long words, and most instructions can use any
of the addressing modes of Table 19.
Table 20. Instruction Set Summary
Mnemonic
Description
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL, ASR
Add Decimal With Extend
Add
Add Address
Add Immediate
Add Quick
Add With Extend
Logical AND
Logical AND Immediate
Arithmetic Shift Left And Right
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
Branch Conditionally
Test Bit And Change
Test Bit And Clear
Test Bit Field And Change
Test Bit Field And Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field And Set
Test Bit Field
Breakpoint
Branch
Test Bit And Set
Branch To Subroutine
Test Bit
CAS
CAS2
CHK
CHK2
CINV(1)
CLR
CMP
CMPA
CMPI
CMPM
CMP2
CPUSH(1)
Compare And Swap Operands
Compare And Swap Dual Operands
Check Register Against Bounds
Check Register Against Upper And Lower Bounds
Invalidate Cache Entries
Clear
Compare
Compare Address
Compare Immediate
Compare Memory To Memory
Compare Register Against Upper And Lower Bounds
Push Then Invalidate Cache Entries
DBCC
DIVS, DIVSL
DIVU, DIVUL
Test Condition, Decrement And Branch
Signed Divide
Unsigned Divide
EOR
EORI
EXG
EXT, EXTB
Logical Exclusive OR
Logical Exclusive OR Immediate
Exchange Registers
Sign Extend
2116A–HIREL–09/02
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Description
The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device.

Features
• 26-42 MIPS Integer Performance
• 3.5-5.6 MFLOPS Floating-Point-Performance
• IEEE 754-Compatible FPU
• Independent Instruction and Data MMUs
• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously
• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
• Multimaster/Multiprocessor Support via Bus Snooping
• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput
• 4G bytes Direct Addressing Range
• Software Support Including Optimizing C Compiler and UNIX® System V Port
• IEEE P 1149-1 Test Mode (JTAG)
• f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W
• The Use of the TS88915T Clock Driver is Suggested

 

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