|TS68040MR1U25A||Third-Generation 32-bit Microprocessor|
|TS68040MR1U25A Datasheet PDF : 49 Pages |
Table 19. Addressing Modes
Date Register Direct
Address Register Direct
Address Register Indirect
Address Register Indirect With Postincrement
Address Register Indirect With Predecrement
Address Register Indirect With Displacement
Register Indirect With Index
Address Register Indirect With Index (8-bit Displacement)
Address Register Indirect With Index (Base Displacement)
(d8, An, Xn)
(bd, An, Xn)
Memory Indirect Postincrement
Memory Indirect Preindexed
([bd, An], Xn, od)
([bd, An, Xn], od)
Program Counter Indirect With Displacement
Program Counter Indirect With Index
PC Indirect With Index (8-bit Displacement)
PC Indirect With Index (Base Displacement
(d8, PC, Xn)
(bd, PC, Xn)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
([bd, PC], Xn, od)
([bd, PC, Xn], od)
d8, d16 =
Data register, D0-D7
Address register, A0-A7
A twos-complement or sign-extended displacement; added as part of the effective address calculation;
size is 8 (d8) or 16 (d16) bits; when omitted, assemblers use a value of zero.
Address or data register used as an index register; form is Xn, SIZE*SCALE, where SIZE is W or L
(indicates index register size) and SCALE is 1, 2, 4 or 8 (index register os multiplied by SCALE); use of
SIZE and or SCALE is optional.
A twos-complement base displacement; when present, size can be 16 or 32 bits.
Outer displacement added as part of effective address calculation after any memory indirection; use is
optional with a size of 16 or 32 bits.
Immediate value of 8, 16 or 32 bits.
Used as indirect address to long-word address.
– Instruction Set Overview
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