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TS68040VFT1U35A View Datasheet(PDF) - Atmel Corporation

Part NameDescriptionManufacturer
TS68040VFT1U35A Third-Generation 32-bit Microprocessor Atmel
Atmel Corporation Atmel
TS68040VFT1U35A Datasheet PDF : 49 Pages
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TS68040
For the subset of the FPU instructions that generate exception traps, the 32-bit floating-
point instruction address register (FPIAR) is loaded with the logical address of an
instruction before the instruction is executed. This address can then be used by a float-
ing-point exception handler to locate a floating-point instruction that has caused an
exception. The move floating-point data register (FMOVE) instruction (to from the
FPCR, FPSR, or FPIAR) and the move multiple data registers (FMOVEN) instruction
cannot generate floating-point exceptions; therefore, these instructions do not modify
the FPIAR. Thus, the FMOVE and FMOVEM instructions can be used to read the
FPIAR in the trap handler without changing the previous value.
Figure 20. Programming Model
31
2116A–HIREL–09/02
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