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TS68040MFU25A View Datasheet(PDF) - Atmel Corporation

Part NameTS68040MFU25A Atmel
Atmel Corporation Atmel
DescriptionThird-Generation 32-bit Microprocessor

TS68040MFU25A Datasheet PDF : 49 Pages
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For the subset of the FPU instructions that generate exception traps, the 32-bit floating-
point instruction address register (FPIAR) is loaded with the logical address of an
instruction before the instruction is executed. This address can then be used by a float-
ing-point exception handler to locate a floating-point instruction that has caused an
exception. The move floating-point data register (FMOVE) instruction (to from the
FPCR, FPSR, or FPIAR) and the move multiple data registers (FMOVEN) instruction
cannot generate floating-point exceptions; therefore, these instructions do not modify
the FPIAR. Thus, the FMOVE and FMOVEM instructions can be used to read the
FPIAR in the trap handler without changing the previous value.
Figure 20. Programming Model
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The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device.

• 26-42 MIPS Integer Performance
• 3.5-5.6 MFLOPS Floating-Point-Performance
• IEEE 754-Compatible FPU
• Independent Instruction and Data MMUs
• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously
• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
• Multimaster/Multiprocessor Support via Bus Snooping
• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput
• 4G bytes Direct Addressing Range
• Software Support Including Optimizing C Compiler and UNIX® System V Port
• IEEE P 1149-1 Test Mode (JTAG)
• f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W
• The Use of the TS88915T Clock Driver is Suggested


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