|TS68040VFT1U35A||Third-Generation 32-bit Microprocessor|
|TS68040VFT1U35A Datasheet PDF : 49 Pages |
registers may be used for word and long-word operations, and all of the 16 general-pur-
pose registers (D0-D7, A0-A7 in Figure 20) may be used as index registers.
The eight, 80-bit, floating-point data registers (FP0-FP7) are analogous to the integer
data registers (D0-D7) of all TS68000 Family processors. Floating-point data registers
always contain extended-precision numbers. All external operands, regardless of the
data format, are converted to extended-precision values before being used in any float-
ing-point calculation or stored in a floating-point data register.
The program counter (PC) usually contains the address of the instruction being exe-
cuted by the TS68040. During instruction execution and exception processing, the
processor automatically increments the contents of the PC or places a new value in the
PC, as appropriate. The status register (SR in the supervisor programming model) con-
tains the condition codes that reflect the results of a previous operation and can be used
for conditional instruction execution in a program. The lower byte of the SR is accessible
in user mode as the condition code register (CCR). Access to the upper byte of the SR
is restricted to the supervisor mode.
As part of exception processing, the vector number of the exception provides an index
into the exception vector table. The base address of the exception vector table is stored
in the vector base register (VBR). The displacement of an exception vector is added to
the value in the VBR when the TS68040 accesses the vector table during exception
Alternate function code registers, SFC and DFC (source and destination), contain 3-bit
function codes. Function codes can be considered extensions of the 32-bit linear
address. Function codes are automatically generated by the processor to select address
spaces for data and program accesses at the user and supervisor modes. The alternate
function code registers are used by certain instructions to explicitly specify the function
codes for various operations. The cache control register (CACR) controls enabling of
the on-chip instruction and data caches of the TS68040.
The supervisor root pointer (SRP) and user root pointer (URP) registers point to the root
of the address translation table tree to be used for supervisor mode and user mode
accesses. The URP is used if FC2 of the logical address is zero, and the SRP is used if
FC2 is one.
The translation control register (TC) enables logical-to-physical address translation and
selects either 4K or 8K page sizes. As shown in Figure 20, there are four transparent
translation registers - ITT0 and ITT1 for instruction accesses and DTT0 and DTT1 for
data accesses. These registers allow portions of the logical address space to be trans-
parently mapped and accessed without the use of resident descriptors in an ATC. The
MMU status register (MMUSR) contains status information from the execution of a
PTEST instruction. The PTEST instruction searches the translation tables for the logical
address as specified by this instruction’s effective address field and the DFC.
The 32-bit floating-point control register (FPCR) contains an exception enable byte that
enables disables traps for each class of floating-point exceptions and a mode byte that
sets the user-selectable modes. The FPCR can be read or written to by the user and is
cleared by a hardware reset or a restore operation of the null state. When cleared, the
FPCR provides the IEEE 754 standard defaults. The floating-point status register
(FPSR) contains a condition code byte, quotient bits, an exception status byte, and an
accrued exception byte. All bits in the FPSR can be read or written by the user. Execu-
tion of most floating-point instructions modifies this register.
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