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TS68040DESC01YCA View Datasheet(PDF) - Atmel Corporation

Part NameTS68040DESC01YCA Atmel
Atmel Corporation Atmel
DescriptionThird-Generation 32-bit Microprocessor
TS68040DESC01YCA Datasheet PDF : 49 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
R suffix
PGA 179
Ceramic Pin Grid Array
Cavity Down
F suffix
CQFP 196
Gullwing Shape Lead
Ceramic Quad Fla Pack
Figure 1. Block Diagram
CONVERT
EXECUTE
WRITE
BACK
FLOATING-
POINT
UNIT
INSTRUCTION
FETCH
DECODE
EFFECTIVE
ADDRESS
CALCULATE
EFFECTIVE
ADDRESS
FETCH
EXECUTE
WRITE
BACK
INTEGER
UNIT
INSTRUCTION DATA BUS
INSTRUCTION
ATC
INSTRUCTION
CACHE
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION
ADDRESS
INSTRUCTION MEMORY UNIT
B
U
S
DATA MEMORY UNIT
DATA
MMU/CACHE/SNOOP
CONTROLLER
C
O
N
T
R
O
L
DATA
L
ADDRESS
E
R
ADDRESS
BUS
DATA
BUS
BUS
CONTROL
SIGNALS
DATA
ATC
DATA
CACHE
OPERAND DATA BUS
2 TS68040
2116A–HIREL–09/02
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Description
The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device.

Features
• 26-42 MIPS Integer Performance
• 3.5-5.6 MFLOPS Floating-Point-Performance
• IEEE 754-Compatible FPU
• Independent Instruction and Data MMUs
• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously
• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
• Multimaster/Multiprocessor Support via Bus Snooping
• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput
• 4G bytes Direct Addressing Range
• Software Support Including Optimizing C Compiler and UNIX® System V Port
• IEEE P 1149-1 Test Mode (JTAG)
• f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W
• The Use of the TS88915T Clock Driver is Suggested

 

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