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TS68040VFT1U35A View Datasheet(PDF) - Atmel Corporation

Part NameDescriptionManufacturer
TS68040VFT1U35A Third-Generation 32-bit Microprocessor Atmel
Atmel Corporation Atmel
TS68040VFT1U35A Datasheet PDF : 49 Pages
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Figure 19. Test Access Port Timing Diagram
Programming Model
The TS68040 integrates the functions of the integer unit, MMU, and FPU. As shown in
Figure 20, the registers depicted in the programming model provide access and control
for the three units. The registers are partitioned into two levels of privilege: user and
supervisor. User programs, executing in the user mode, can only use the resources of
the user model. System software, executing in the supervisor mode, has unrestricted
access to all processor resources.
The integer portion of the user programming model, consisting of 16, general-purpose,
32-bit registers and two control registers, is the same as the user programming model of
the TS68030. The TS68040 user programming model also incorporates the TS68882
programming model consisting of eight, floating-point, 80-bit data registers, a floating-
point control register, a floating-point status register, and a floating-point instruction
address register.
The supervisor programming model is used exclusively by TS68040 system program-
mers to implement operating system functions, I/O control, and memory management
subsystems. This supervisor/user distinction in the TS68000 architecture was carefully
planned so that all application software can be written to execute in the nonprivileged
user mode and migrate to the TS68040 from any TS68000 platform without modifica-
tion. Since system software is usually modified by system designers when porting to a
new design, the control features are properly placed in the supervisor programming
model. For example, the transparent translation registers of the TS68040 can only be
read or written by the supervisor software; the programming resources of user applica-
tion programs are unaffected by the existence of the transparent translation registers
Registers D0-D7 are data registers containing operands for bit and bit field (1- to 32-bit),
byte (8-bit), word (16-bit), long-word (32-bit), and quad-word (64-bit) operations. Regis-
ters A0-A6 and the stack pointer registers (user, interrupt, and master) are address
registers that may be used as software stack pointers or base address registers. Regis-
ter A7 is the user stack pointer in user mode, and is either the interrupt or master stack
pointer (A7’ or A7’’) in supervisor mode. In supervisor mode, the active stack pointer
(interrupt or master) is selected based on a bit in the status register (SR). The address
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