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TS68040VF1D/T35A View Datasheet(PDF) - Atmel Corporation

Part NameTS68040VF1D/T35A Atmel
Atmel Corporation Atmel
DescriptionThird-Generation 32-bit Microprocessor
TS68040VF1D/T35A Datasheet PDF : 49 Pages
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Table 15. Input AC Timing Specifications (Figure 9 to Figure 15) (Continued)
-55°C TC TJmax; 4.75V VCC 5.25V unless otherwise specified(1)(2)(3)(4)
25 MHz
33 MHz
Num Characteristic
Min. Max. Min. Max. Unit
44c TTn Valid to BCLK (Setup)
6
8.5
ns
44d R/W Valid to BCLK (Setup)
6
5
ns
44e SCn Valid to BCLK (Setup)
10
11
ns
45 BCLK to Address SIZn, TTn, R/W, SCn Invalid (Hold)
2
2
ns
46 TS Valid to BCLK (Setup)
5
9
ns
47 BCLK to TS Invalid (Hold)
2
2
ns
49 BCLK to BB High Impedance (68040 Assumes Bus Mastership)
9
9
ns
51 RSTI Valid to BCLK
5
4
ns
52
53
54
Notes:
BCLK to RSTI Invalid
2
2
ns
Mode Select Setup to RSTI Negated(4)
20
20
ns
RSTI Negated to Mode Selects Invalid(4)
2
2
ns
1. All testing to be performed using worst-case test conditions unless otherwise specified.
2. The following pins are active low: AVEC, BG, BS, BR, CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, MDIS, MI,
RST0, RSTI, TA, TBI, TCI, TEA, TIP, TRST, TS and W of R/W.
3. Maximum operating junction temperature (TJ) = +125°. Minimum case operating temperature (TC) = -55°. This device is not
tested at TC = +125°. Testing is performed by setting the junction temperature TJ = +125°and allowing the case and ambient
temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.
4. The levels on CDIS, MDIS, and the IPL2-IPL0 signals enable or disable the multiplexed bus mode, data latch enable mode,
and driver impedance selection respectively.
22 TS68040
2116A–HIREL–09/02
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Description
The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device.

Features
• 26-42 MIPS Integer Performance
• 3.5-5.6 MFLOPS Floating-Point-Performance
• IEEE 754-Compatible FPU
• Independent Instruction and Data MMUs
• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously
• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
• Multimaster/Multiprocessor Support via Bus Snooping
• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput
• 4G bytes Direct Addressing Range
• Software Support Including Optimizing C Compiler and UNIX® System V Port
• IEEE P 1149-1 Test Mode (JTAG)
• f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W
• The Use of the TS88915T Clock Driver is Suggested

 

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