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TS68040DESC01YCA View Datasheet(PDF) - Atmel Corporation

Part NameDescriptionManufacturer
TS68040DESC01YCA Third-Generation 32-bit Microprocessor Atmel
Atmel Corporation Atmel
TS68040DESC01YCA Datasheet PDF : 49 Pages
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Figure 8. Clock Input Timing
Table 14. Output AC Timing Specifications(1) (Figure 9 to Figure 15)
These output specifications are only for 25 MHz. They must be scaled for lower operating frequencies. Refer to
TS6804DH/AD for further information. -55°C TC TJmax; 4.75V VCC 5.25V unless otherwise specified.(2)(3)(4)
25 MHz
33 MHz
Large
Buffer(1)
Small
Buffer(1)
Large
Buffer(1)
Small
Buffer(1)
Num Characteristic
Min Max Min Max Min Max Min Max Unit
11 BCLK to address CIOUT, LOCK, LOCKE,
R/W, SIZn, TLN, TMn, UPAn valid(5)
9
21
9
30 6.50 18 6.50 25
ns
12 BCLK to output invalid (output hold)
9
9
6.50
6.50
ns
13 BCLK to TS valid
9
21
9
30 6.50 18 6.50 25
ns
14 BCLK to TIP valid
18 BCLK to data-out valid(6)
19 BCLK to data-out invalid (output hold)(6)
20 BCLK to output low impedance(5)(6)
9
21
9
30 6.50 18 6.50 25
ns
9
23
9
32 6.50 20 6.50 27
ns
9
9
6.50
6.50
ns
9
9
6.50
6.50
ns
21 BCLK to data-out high impedance
26 BCLK to multiplexed address valid(5)
27 BCLK to multiplexed address driven(5)
9
20
9
20 6.50 17 6.50 17
ns
19
31
19
40
14
26
14
33
ns
19
19
14
14
ns
28 BCLK to multiplexed address high
impedance(5)(6)
29 BCLK to multiplexed data driven(6)
30 BCLK to multiplexed data valid(6)
9
18
9
18 6.50 15 6.50 15
ns
19
19
14
20
14
20
ns
19
33
19
42
14
28
14
35
ns
38 BCLK to address CIOUT, LOCK, LOCKE,
R/W, SIZn, TS, TLNn, TMn, TTn, UPAn high
impedance(5)
9
18
9
18 6.50 15 6.50 15
ns
39 BCLK to BB, TA, TIP high impedance
19
28
19
28
14
23
14
23
ns
40 BCLK to BR, BB valid
9
21
9
30 6.50 18 6.50 25
ns
43 BCLK to MI valid
9
21
9
30 6.50 18 6.50 25
ns
48 BCLK to TA valid
9
21
9
30 6.50 18 6.50 25
ns
50 BCLK to IPEND, PSTn, RSTO valid
9
21
9
30 6.50 18 6.50 25
ns
20 TS68040
2116A–HIREL–09/02
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