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TS68040MFTU35A View Datasheet(PDF) - Atmel Corporation

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TS68040MFTU35A Datasheet PDF : 49 Pages
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26-42 MIPS Integer Performance
3.5-5.6 MFLOPS Floating-Point-Performance
IEEE 754-Compatible FPU
Independent Instruction and Data MMUs
4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed
32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
Multimaster/Multiprocessor Support via Bus Snooping
Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize
4G bytes Direct Addressing Range
Software Support Including Optimizing C Compiler and UNIX® System V Port
IEEE P 1149-1 Test Mode (JTAG)
f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W
The Use of the TS88915T Clock Driver is Suggested
The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-
bit microprocessors. The TS68040 is a virtual memory microprocessor employing
multiple, concurrent execution units and a highly integrated architecture to provide
very high performance in a monolithic HCMOS device. On a single chip, the TS68040
integrates a 68030-compatible integer unit, an IEEE 754-compatible floating-point unit
(FPU), and fully independent instruction and data demand-paged memory manage-
ment units (MMUs), including 4K bytes independent instruction and data caches. A
high degree of instruction execution parallelism is achieved through the use of multi-
ple independent execution pipelines, multiple internal buses, and a full internal
Harvard architecture, including separate physical caches for both instruction and data
accesses. The TS68040 also directly supports cache coherency in multimaster appli-
cations with dedicated on-chip bus snooping logic.
The TS68040 is user-object-code compatible with previous members of the TS68000
Family and is specifically optimized to reduce the execution time of compiler-gener-
ated code. The 68040 HCMOS technology, provides an ideal balance between speed,
power, and physical device size.
Figure 1 is a simplified block diagram of the TS68040. Instruction execution is pipe-
lined in both the integer unit and FPU. Independent data and instruction MMUs control
the main caches and the address translation caches (ATCs). The ATCs speed up log-
ical-to-physical address translations by storing recently used translations. The bus
snooper circuit ensures cache coherency in multimaster and multiprocessing
• MIL-STD-883
• DESC. Drawing 5962-93143
• Atmel Standards
Rev. 2116A–HIREL–09/02

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