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TS68040VFTU/T25A View Datasheet(PDF) - Atmel Corporation

Part Name
Description
MFG CO.
TS68040VFTU/T25A
Atmel
Atmel Corporation Atmel
TS68040VFTU/T25A Datasheet PDF : 49 Pages
Output Buffer Mode
TS68040
The 68040 is capable of resetting to enable for a combination of either large buffers or
small buffers on the outputs of the miscellaneous control signals, data bus, and address
bus/transfer attribute pins. The large buffers offer quicker output times, which allow for
an easier logic design. However, they do so by driving about 11 times as much current
as the small buffers (refer to TS68040 Electrical specifications for current output). The
designer should consider whether the quicker timings present enough advantage to jus-
tify the additional consideration to the individual signal terminations, the die power
consumption, and the required cooling for the device. Since the TS68040 can be pow-
ered-up in one of eight output buffer modes upon reset, the actual maximum power
consumption for TS68040 rated at a particular maximum operating frequency is depen-
dent upon the power up mode. Therefore, the TS68040 is rated at a maximum power
dissipation for either the large buffers or small buffers at a particular frequency (refer to
TS68040 Electrical specifications). This allows the possibility of some of the thermal
management to be controlled upon reset. The following equation provides a rough
method to calculate the maximum power consumption for a chosen output buffer mode:
PD = PDSB + (PDLB - PDSB) · (PINSLB/PINSCLB)
(1)
where:
PD
= Max. power dissipation for output buffer mode
selected
PDSB
= Max. power dissipation for small buffer mode
(all outputs)
PDLB
= Max. power dissipation for large buffer mode
(all outputs)
PINSLB = Number of pins large buffer mode
PINSCLB = Number of pins capable of the large buffer
mode
Table 6 shows the simplified relationship on the maximum power dissipation for eight
possible configurations of output buffer modes.
Table 6. Maximum Power Dissipation for Output Buffer Mode Configurations
Output Configuration
Maximum Power Dissipation
Address Bus and
Misc. Control
Data Bus
Transfer Attrib.
Signals
PD
Small Buffer
Small Buffer
Small Buffer
Small Buffer
Large Buffer
Large Buffer
Large Buffer
Large Buffer
Small Buffer
Small Buffer
Large Buffer
Large Buffer
Small Buffer
Small Buffer
Large Buffer
Large Buffer
Small Buffer
Large Buffer
Small Buffer
Large Buffer
Small Buffer
Large Buffer
Small Buffer
Large Buffer
PDSB
PDSB + (PDLB - PDSB) · 13%
PDSB + (PDLB - PDSB) · 52%
PDSB + (PDLB - PDSB) · 65%
PDSB + (PDLB - PDSB) · 35%
PDSB + (PDLB - PDSB) · 48%
PDSB + (PDLB - PDSB) · 87%
PDSB + (PDLB - PDSB) · 100%
11
2116A–HIREL–09/02
 

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