|TS68020MF1B||HCMOS 32-bit Virtual Memory Microprocessor|
|TS68020MF1B Datasheet PDF : 45 Pages |
Table 1. Signal Index
External Cycle Start
Operand Cycle Start
Data Buffer Enable
Data Transfer and Size
Interrupt Priority Level
Bus Grant Acknowledge
32-bit Address Bus Used to address any of 4, 294, 967, 296 bytes.
32-bit Data Bus Used to Transfer 8, 16, 24 or 32 bits of Data Per Bus Cycle.
3-bit Function Case Used to Identify the Address Space of Each Bus Cycle.
Indicates the Number of Bytes Remaining to be Transferred for this Cycle.
These Signals, Together with A0 And A1, Define the Active Sections of the
Provides an Indicator that the Current Bus Cycle is Part of an Indivisibleread-
Provides an Indication that a Bus Cycle is Beginning.
Identical Operation to that of ECS Except that OCS Is Asserted Only During
the First Bus Cycle of an Operand Transfer.
Indicates that a Valid Address is on The Bus.
Indicates that Valid Data is to be Placed on the Data Bus by an External
Device or has been Laced on the Data Bus by the TS68020.
Defines the Bus Transfer as an MPU Read or Write.
Provides an Enable Signal for External Data Buffers.
Bus Response Signals that Indicate the Requested Data Transfer Operation
is Completed. In Addition, these Two Lines Indicate the Size of the External
Bus Port on a Cycle-by-cycle Basis.
Dynamically Disables the On-chip Cache to Assist Emulator Support.
Provides an Encoded Interrupt Level to the Processor.
Requests an Autovector During an Interrupt Acknowledge Cycle.
Indicates that an Interrupt is Pending.
Indicates that an External Device Requires Bus Mastership.
Indicates that an External Device may Assume Bus Mastership.
Indicates that an External Device has Assumed Bus Mastership.
Indicates that the Processor Should Suspend Bus Activity.
Indicates an Invalid or Illegal Bus Operation is Being Attempted.
Clock Input to the Processor.
+5-volt ± 10% Power Supply.
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