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TS68020DESC02XA View Datasheet(PDF) - Atmel Corporation

Part NameDescriptionManufacturer
TS68020DESC02XA HCMOS 32-bit Virtual Memory Microprocessor Atmel
Atmel Corporation Atmel
TS68020DESC02XA Datasheet PDF : 45 Pages
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On-chip Instruction
Cache
TS68020 Cache Goals
The TS68020 provides an extension to the exception stacking process. If the M bit in the
status register is set, the master stack pointer (MSP) is used for all task related excep-
tions. When a non-task exception occurs (i.e., an interrupt), the M bit is cleared and the
interrupt stack pointer (ISP) is used. This feature allows all the task’s stack area to be
carried within a single processor control block and new tasks may be initiated by simply
reloading the master stack pointer and setting the M bit.
The fourth and last step of the exception processing is the same for all exceptions. The
exception vector offset is determined by multiplying the vector number by four. This off-
set is then added to the contents of the vector base register (VBR) to determine the
memory address of the exception vector. The new program counter value is fetched
from the exception vector. The instruction at the address given in the exception vector is
fetched, and the normal instruction decoding and execution is started.
Studies have shown that typical programs spend most of their execution time in a few
main routines or tight loops. This phenomenon is known as locality of reference, and
has an impact on performance of the program. The TS68020 takes limited advantage of
this phenomenon in the form of its loop mode operation which allows certain instruc-
tions, when coupled with the DBcc instruction, to execute without the overhead of
instruction fetches. In effect, this is a three word cache. Although the cache hardware
has been supplied in a full range of computer systems for many years, technology now
allows this feature to be integrated into the microprocessor.
There were two primary goals for the TS68020 microprocessor cache. The first design
goal was to reduce the processor external bus activity. In a given TS68000 system, the
TS68000 processor will use approximately 80 to 90 percent (for greater) of the available
bus bandwidth. This is due to its extremely efficient perfecting algorithm and the overall
speed of its internal architecture design. Thus, in an TS68000 system with more than
one bus master (such as a processor and DMA device) or in a multiprocessor system,
performance degradation can occur due to lack of available bus bandwidth. Therefore,
an important goal for an TS68020 on-chip cache was to provide a substantial increase
in the total available bus bandwidth.
The second primary design goal was to increase effective CPU throughput as larger
memory sizes or slower memories increased average access time. By placing a high
speed cache between the processor and the rest of the memory system, the effective
access time now becomes:
tACC = h**tCACHE = (1 - h)*text
where tACC is the effective system access time, tCACHE is the cache access time, text is
the access time of the rest of the system, and h is the hit ratio or the percentage of time
that the data is found in the cache. Thus, for a given system design, an TS68020 on-
chip cache provides a substantial CPU performance increase, or allows much slower
and less expensive memories to be used for the same processor performance.
The throughput increase in the TS68020 is gained in two ways. First, the TS68020
cache is accessed in two clock cycles versus the three cycles (minimum) required for an
external access. Any instruction fetch that is currently resident in the cache will provide
a 33% improvement over the corresponding external access.
38 TS68020
2115A–HIREL–07/02
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