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TS68020DESC02XA View Datasheet(PDF) - Atmel Corporation

Part NameDescriptionManufacturer
TS68020DESC02XA HCMOS 32-bit Virtual Memory Microprocessor Atmel
Atmel Corporation Atmel
TS68020DESC02XA Datasheet PDF : 45 Pages
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Co-processor Protocol
Table 11. Co-processor Primitives (Continued)
General Operand Transfer
Evaluate and Pass (Ea.)
Evaluate (Ea.) and Transfer Data
Write to Previously Evaluated (Ea.)
Take Address and Transfer Data
Transfer to/from Top of Stack
Register Transfer
Transfer CPU Register
Transfer CPU Control Register
Transfer Multiple CPU Registers
Transfer Multiple Co-processor Registers
Transfer CPU SR and/or ScanPC
Up to eight processors are supported in a single system with a system-unique co-pro-
cessor identifier encoded in the co-processor instruction. When accessing a co-
processor, the TS68020 executes standard read and write bus cycle in CPU address
space, as encoded by the function codes, and places the co-processor identifier on the
address bus to be used by chip-select logic to select the particular co-processor. Since
standard bus cycle are used to access the co-processor, the co-processor may be
located according to system design requirements, whether it be located on the micro-
processor local bus, on another board on the system bus, or any other place where the
chip-select and co-processor protocol using standard TS68000 bus cycles can be
supported.
Interprocessor transfers are all initiated by the main processor during co-processor
instruction execution. During the processing of a co-processor instruction, the main pro-
cessor transfers instruction information and data to the associated co-processor, and
receives data, requests, and status information from the co-processor. These transfers
are all based on the TS68000 bus cycles.
The typical co-processor protocol which the main processor follows is:
a) The main processor initiates the communications by writing command information to
a location in the co-processor interface.
b) The main processor reads the co-processor response to that information.
1) The response may indicate that the co-processor is busy, and the main processor
should again query the co-processor. This allows the main processor and co-pro-
cessor to synchronize their concurrent operations.
2) The response may indicate some exception condition; the main processor
acknowledges the exception and begins exception processing.
3) The response may indicate that the co-processor needs the main processor to
perform some service such as transferring data to or from the co-processor. The co-
processor may also request that the main processor query the co-processor again
after the service is complete.
4) The response may indicate that the main processor is not needed for further pro-
cessing of the instruction. The communication is terminated, and the main
processor is free to begin execution of the next instruction. At this point in the co-
processor protocol, as the main processor continues to execute the instruction
stream, the main processor may operate concurrently with the co-processor.
36 TS68020
2115A–HIREL–07/02
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