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|Description||HCMOS 32-bit Virtual Memory Microprocessor|
|TS68020DESC02XA Datasheet PDF : 45 Pages |
The TS68020 will always transfer the maximum amount of data on all bus cycles; i.e., it
always assumes the port is 32-bit wide when beginning the bus cycle. In addition, the
TS68020 has no restrictions concerning alignment of operands in memory; long word
operands need not be aligned on long word address boundaries. When misaligned data
requires multiple bus cycles, the TS68020 aligned data requires multiple bus cycles, the
TS68020 automatically runs the minimum number of bus cycles.
The co-processor interface is a mechanism for extending the instruction set of the
TS68000 Family. Examples of these extensions are the addition of specialized data
operands for the existing data types or, for the case of the floating point, the inclusion of
new data types and operations for them as implemented by the TS68881 and TS68882
floating point co-processors.
The programmer’s model for the TS68000 Family of microprocessors is based on
sequential, non-concurrent instruction execution. This means each instruction is com-
pletely executed prior to the beginning of the next instruction. Hence, instructions do not
operate concurrently in the programmer’s model. Most microprocessors implement the
sequential model which greatly simplifies the programmer responsibilities since
sequencing control is automatic and discrete.
The TS68000 co-processor interface is designed to extend the programmer’s model and
it provides full support for the sequential, non-concurrent instruction execution model.
Hence, instruction execution by the co-processor is assumed to not overlap with instruc-
tion execution with the main microprocessor. Yet, the TS68000 co-processor interface
does allow concurrent operation when concurrency can be properly accommodated. For
example, the TS68881 or TS68882 floating-point co-processor will allow the TS68020 to
proceed executing instruction while the co-processor continues a floating-point opera-
tion, up to the point that the TS68020 sends another request to the co-processor.
Adhering to the sequential execution model, the request to the co-processor continues a
floating-point operation, up to the co-processor completes each TS68881 and TS68882
instruction before it starts the next, and the TS68020 is allowed to proceed as it can in a
co-processors are divided into two types by their bus utilization characteristics. A co-
processor is a DMA co-processor if it can control the bus independent of the main pro-
cessor. A co-processor is a non-DMA co-processor if it does not have the capability of
controlling the bus. Both co-processor types utilize the same protocol and main proces-
sor resources. Implementation of a co-processor as a DMA or non-DMA type is based
primarily on bus bandwidth of the co-processor, performance, and cost issues.
The communication protocol between the main processor and the co-processor neces-
sary to execute a co-processor instruction is based on a group of co-processor interface
registers (Table 10) which are defined for the TS68000 Family co-processor interface.
The TS68020 hardware uses standard TS68000 asynchronous bus cycles to access the
registers. Thus, the co-processor doesn’t require a special bus hardware; the bus inter-
face implemented by a co-processor for its interface register set must only satisfy the
TS68020 address, data, and control signal timing to guarantee proper communication
with the main processor. The TS68020 implements the communication protocol with all
co-processors in hardware (and microcode) and handles all operations automatically so
the programmer is only concerned with the instructions and data types provided by the
co-processor as extensions to the TS68020 instruction set and data types.
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