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TS68020DESC02XA View Datasheet(PDF) - Atmel Corporation

Part NameTS68020DESC02XA Atmel
Atmel Corporation Atmel
DescriptionHCMOS 32-bit Virtual Memory Microprocessor
TS68020DESC02XA Datasheet PDF : 45 Pages
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TS68020
Bit Field Operation
The TS68020 supports variable length bit field operations up to 32-bit. A bit field may
start in any bit position and span any address boundary for the full length of the bit field,
up to the 32-bit maximum. The bit field insert (BFINS) inserts a value into a field. Bit field
extract unsigned (BFEXTU) and bit field extract signed (BFEXTS) extract an unsigned
or signed value from the field. BFFFO finds the first bit in a bit field that is set. To com-
plement the TS68000 bit manipulation instruction, there are bit field change, clear, set
and test instructions (BFCHG, BFCLR, BFSET, BFTST). Using the on-chip barrel
shifter, the bit and bit field instructions are very fast and particularly useful in applica-
tions using packed bits and bit fields, such as graphics and communications.
Binary Coded Decimal (BCD)
Support
The TS68000 Family supports BCD operations including add, subtract, and negation.
The TS68020 adds the PACK and UNPACK operations for BCD conversions to and
from binary form as well as other conversions, e.g., ASCII and EBCDIC. The PACK
instruction reduces two bytes of data into a single byte while UNPACK reverses the
operation.
Bounds Checking
Previous 68000 Family members offer variable bounds checking only on the upper limit
of the bound. The underlying assumption is that the lower bound is zero. This is
expanded on the TS68020 by providing two new instructions, CHK2 and CMP2. These
instructions allow checking and comparing of both the upper and lower bounds. These
instructions may be either signed or unsigned. The CMP2 instructions sets the condition
codes upon completion while the CHK2 instruction, in addition to setting the condition
codes, will take a system trap if either boundary condition is exceeded.
System Traps
Three additions have been made to the system trap capabilities of the TS68020. The
current TRAPV (trap on overflow) instruction has been expanded to a TRAPcc format
where any condition code is allowed to be the trapping condition. And, the TRAPcc
instruction is expanded to optionally provide one or two additional words following the
trap instruction so user-specified information may be presented to the trap handler.
These additional words can be used when needed to provide simple error codes or
debug information for interactive runtime debugging or post-mortem program dumps.
Compilers may provide direction to run-time execution routines towards handling of spe-
cific conditions.
The breakpoint instruction, BKPT, is used to support the program breakpoint function for
debug monitors and real-time in-circuit or hardware emulators, and the operation will be
dependent on the actual system implementation. Execution of this instruction causes
the TS68020 to run a breakpoint acknowledge bus cycle, with a 3-bit breakpoint identi-
fier placed on address lines A2, A3, and A4. This 3-bit identifier permits up to eight
breakpoints to be easily differentiated. The normal response to the TS68020 is an oper-
ation word (typically an instruction, originally replaced by the debugger with the
breakpoint instruction) placed on the data lines by external debugger hardware and the
breakpoint acknowledge cycle properly terminated. The TS68020 then executes this
operation word in place of the breakpoint instruction. The debugger hardware can count
the number of executions of each breakpoint and halt execution after a pre-determined
number of cycles.
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2115A–HIREL–07/02
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Description
The TS68020 is the first full 32-bit implementation of the TS68000 family of microprocessors. Using HCMOS technology, the TS68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.

Features
• Object Code Compatible with Earlier TS68000 Microprocessors
• Addressing Mode Extensions for Enhanced Support of High Level Languages
• New Bit Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics
• Fast on-chip Instruction Cache Speed Instructions and Improves Bus Bandwidth
• Co-processor Interface to Companion 32-bit Peripherals: TS68881 and TS68882 Floating Point Co-processors
• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions to be Executed Concurrently
• High Performance Asynchronous Bus in Non-multiplexed and Full 32 Bits
• Dynamic Bus Sizing Efficiently Supports 8-, 16-, 32-bit Memories and Peripherals
• Full Support of Virtual Memory and Virtual Machine
• Sixteen 32-bit General-purpose Data and Address Registers
• Two 32-bit Supervisor Stack Pointers and 5 Special Purpose Control Registers
• 18 Addressing Modes and 7 Data Types
• 4-Gbyte Direct Addressing Range
• Processor Speed: 16.67 MHz - 20 MHz - 25 MHz
• Power Supply: 5.0 VDC ± 10%

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