|TS68020MF1B/C20||HCMOS 32-bit Virtual Memory Microprocessor|
|TS68020MF1B/C20 Datasheet PDF : 45 Pages |
The TS68020 is a high-performance 32-bit microprocessor. It is the first microprocessor
to have evolved from a 16-bit machine to a full 32-bit machine that provides 32-bit
address and data buses as well as 32-bit internal structures. Many techniques were uti-
lized to improve performance and at the same time maintain compatibility with other
processors of the TS68000 Family. Among the improvements are new addressing
modes which better support high-level language structures, an expanded instruction set
which provides 32-bit operations for the limited cases not supported by the TS68000
and several new instructions which support new data types. For special-purpose appli-
cations when a general-purpose processor alone is not adequate, a co-processor
interface is provided.
The TS68020 is a high-performance microprocessor implemented in HCMOS, low
power, small geometry process. This process allows CMOS and HMOS (high density
NMOS) gates to be combined on the same device. CMOS structures are used where
speed and low power is required, and HMOS structures are used where minimum sili-
con area is desired. This technology enables the TS68020 to be very fast while
consuming less power (less than 1.5 watts) and still have a reasonably small die size. It
utilizes about 190.000 transistors, 103.000 of which are actually implemented. The
package is a pin-grid array (PGA) with 114 pins, arranged 13 pins on a side with a
depopulated center and 132 pins ceramic quad flat pack.
Figure 1 is a block diagram of the TS68020. The processor can be divided into two main
sections: the bus controller and the micromachine. This division reflects the autonomy
with which the sections operate.
Figure 1. TS68020 Block Diagram
The bus controller consists of the address and data pads and multiplexers required to
support dynamic bus sizing, a macro bus controller which schedules the bus cycles on
the basis of priority with two state machines (one to control the bus cycles for operated
accesses and the other to control the bus cycles for instruction accesses), and the
instruction cache with its associated control.
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