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TS68020DESC02XA View Datasheet(PDF) - Atmel Corporation

Part NameDescriptionManufacturer
TS68020DESC02XA HCMOS 32-bit Virtual Memory Microprocessor Atmel
Atmel Corporation Atmel
TS68020DESC02XA Datasheet PDF : 45 Pages
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The TS68000 Family processors distinguish address spaces as supervisor / used and
program/data. These four combinations are specified by the function code pins
(FC0/FC1/FC2) during bus cycles, indication the particular address space. Using the
function codes, the memory sub-system can distinguish between authorized access
(supervisor mode is privileged access) and unauthorized access (user mode may not
have access to supervisor program or data areas). To support the full privileges of the
supervisor, the alternate function code registers allow the supervisor to specify an
access to user program or data areas by preloading the SFC/DFC registers
appropriately.
The cache registers (control — CACR, address — CAAR) allow software manipulation
of the on-chip instruction cache. Control and status accesses to the instruction cache
are provided by the cache control register (CACR), while the cache address register
(CAAR) holds the address for those cache control functions that require an address.
Figure 19. User Programming Model
24 TS68020
2115A–HIREL–07/02
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