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TS68020DESC04XA View Datasheet(PDF) - Atmel Corporation

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TS68020DESC04XA
Atmel
Atmel Corporation Atmel
TS68020DESC04XA Datasheet PDF : 45 Pages
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TS68020
Table 6. Dynamic Electrical Characteristics (Continued)
Symbol Parameter
Interval
Number
68020-16
Min Max
68020-20
Min Max
68020-25
Min Max
Unit
Notes
f
Frequency of Operation
8.0 16.67 12.5 20.0 12.5 25 MHz
tRADC
R/W Asserted to Data Bus Impedance
55
30
25
20
(11)
Change
tHRPW
RESET Pulse Width (Reset Instruction)
56
512
tBNHN
BERR Negated to HALT Negated
(Rerun)
57
0
512
512
0
0
Clks
(11)
ns
(11)
tGANBD BGACK Negated to Bus Driven
58
1
1
1
Clks
(10)(11)
tGNBD
BG Negated to Bus Driven
59
1
1
1
Clks
(10)(11)
Notes: 1. This number can be reduced to 5 nanoseconds if the strobes have equal loads.
2. If the asynchronous setup time (= 47) requirements are satisfied, the DSACKx low to data setup time (= 31) and DSACKx
low to BERR low setup time (= 48) can be ignored. The data must only satisfy the data in to clock low setup time (= 27) for
the following clock cycle, BERR must only satisfy the late BERR low to clock setup time (= 27) for the following clock cycle.
3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or DSACK1 to DSACK0
asserted pattern = 47 must be met by DSACK0 and DSACK1.
4. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous input setup time (= 47).
5. DBEN may stay asserted on consecutive write cycles.
6. Actual value depends on the clock input waveform.
7. This pattern indicates the minimum high time for ECS and OCS in the event of an internal cache hit followed immediately by
a cache miss or operand cycle.
8. This specification guarantees operations with the 68881 co-processor, and defines a minimum time for DS negated to AS
asserted (= 13A). Without this parameter, incorrect interpretation of = 9A and = 15 would indicate that the 68020 does not
meet 68881 requirements.
9. This pattern allows the systems designer to guarantee data hold times on the output side of data buffers that have output
enable signals generated with DBEN.
10. Guarantees that an alternate bus master has stopped driving the bus when the 68020 regains control of the bus after an
arbitration sequence.
11. Cannot be tested. Provided for system design purposes only.
12. Tcase = -55°C and +130°C in a Power off condition under Thermal soak for 4 minutes or until thermal equilibrium. Electrical
parameters are tested “instant on” 100 m sec. after power is applied.
13. All outputs unload except for load capacitance. Clock = fmax,
LOW: HALT, RESET
HIGH: DSACK0, DSACK1, CDIS, IPL0-IPL2, DBEN, AVEC, BERR.
13
2115A–HIREL–07/02
 

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