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TS68020DESC02XA View Datasheet(PDF) - Atmel Corporation

Part NameTS68020DESC02XA Atmel
Atmel Corporation Atmel
DescriptionHCMOS 32-bit Virtual Memory Microprocessor
TS68020DESC02XA Datasheet PDF : 45 Pages
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TS68020
Dynamic (Switching)
Characteristics
The limits and values given in this section apply over the full case temperature range -
55°C to +125°C and VCC in the range 4.5V to 5.5V VIL = 0.5V and VIH = 2.4V (See also
note 12 and 13). The INTERVAL numbers refer to the timing diagrams. See Figure 5,
Figure 9 and Figure 12.
Table 6. Dynamic Electrical Characteristics
Symbol
tCPW
tCHAV
tCHEV
tCHAZX
tCHAZn
tCLSA
tSTSA
tECSA
tOCSA
tEOCSN
tAVSA
tCLSN
tCLEN
tSNAI
tSWA
tSWAW
tSN
tSNSA
tCSZ
tSNRN
tCHRH
tCHRL
tRAAA
tRASA
tCHDO
tSNDI
tDNDBN
Parameter
Clock Pulse Width
Clock High to Address/FC/Size/RMC
Valid
Clock High to ECS, OCS Asserted
Clock High to Address/Data/FC/RMC/
Size High Impedance
Clock High to Address/FC/Size/RMC
Invalid
Clock Low to AS, DS Asserted
AS to DS Assertion (Read)(Skew)
ECS Width Asserted
OCS Width Asserted
ECS, OCS Width Negated
Address/FC/Size/RMC Valid to AS
Asserted (and DS Asserted, Read)
Clock Low to AS, DS Negated
Clock Low to ECS/OCS Negated
AS, DS Negated to Address/FC/
Size/RMC Invalid
AS (and DS, Read) Width Asserted
DS Width Asserted, Write
AS, DS Width Negated
DS Negated to AS Asserted
Clock High to AS/DS/R/W/DBEN High
Impedance
AS, DS Negated to R/W High
Clock High to R/W High
Clock High to R/W Low
R/W High to AS Asserted
R/W Low to DS Asserted (Write)
Clock High to Data Out Valid
AS, DS Negated to Data Out Valid
DS Negated to DBEN Negated (Write)
Interval
Number
2,3
6
68020-16
Min Max
24
95
0
30
68020-20
Min Max
20 54
0
25
68020-25
Min Max
19 61
0
25
6A
0
20
0
15
0
12
7
0
60
0
50
0
40
8
0
0
0
9
3
30
3
25
3
18
9A
-15
15 -10 10 -10 10
10
20
15
15
10A
20
15
15
10B
15
10
5
11
15
10
6
12
0
30
0
25
0
15
12A
0
30
0
25
0
15
13
15
10
10
14
100
85
70
14A
40
38
30
15
40
38
30
15A
35
30
25
16
60
50
40
17
15
10
10
18
0
30
0
25
0
20
20
0
30
0
25
0
20
21
15
10
5
22
75
60
50
23
30
25
25
25
15
10
5
25A
15
10
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(11)
(1)
(11)
(6)
(11)
(8)
(11)
(6)
(6)
(6)
(6)
(9)
11
2115A–HIREL–07/02
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Description
The TS68020 is the first full 32-bit implementation of the TS68000 family of microprocessors. Using HCMOS technology, the TS68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.

Features
• Object Code Compatible with Earlier TS68000 Microprocessors
• Addressing Mode Extensions for Enhanced Support of High Level Languages
• New Bit Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics
• Fast on-chip Instruction Cache Speed Instructions and Improves Bus Bandwidth
• Co-processor Interface to Companion 32-bit Peripherals: TS68881 and TS68882 Floating Point Co-processors
• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions to be Executed Concurrently
• High Performance Asynchronous Bus in Non-multiplexed and Full 32 Bits
• Dynamic Bus Sizing Efficiently Supports 8-, 16-, 32-bit Memories and Peripherals
• Full Support of Virtual Memory and Virtual Machine
• Sixteen 32-bit General-purpose Data and Address Registers
• Two 32-bit Supervisor Stack Pointers and 5 Special Purpose Control Registers
• 18 Addressing Modes and 7 Data Types
• 4-Gbyte Direct Addressing Range
• Processor Speed: 16.67 MHz - 20 MHz - 25 MHz
• Power Supply: 5.0 VDC ± 10%

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