SLVSB30B – SEPTEMBER 2011 – REVISED AUGUST 2013
Layout is a critical portion of PMIC designs.
• Place tracing for output voltage and LX on the top layer and an inner power plane for VIN.
• Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with
• The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass
capacitor, the output filter capacitor and directly under the TPS652510 device to provide a thermal path from
the PowerPad land to ground.
• For operation at full rated load, the top side ground area together with the internal ground plane, must provide
adequate heat dissipating area.
• There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching
node, the output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
• The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.
Try to minimize this conductor length while maintaining adequate width.
• The compensation should be as close as possible to the CMPx pins. The CMPx and ROSC pins are sensitive
to noise so the components associated to these pins should be located as close as possible to the IC and
routed with minimal lengths of trace.
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Product Folder Links: TPS652510
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