SLVSB30B – SEPTEMBER 2011 – REVISED AUGUST 2013
Figure 38 shows the (peak) inductor current limit for Buck 3. The typical limit can be approximated with the
Figure 38. Buck 3
The current limit should be set by using either the TYP or MIN line. If using the TYP line, ensure that limit trips at
the MIN line are acceptable for your application. When setting high-side current limit to large current values,
ensure that the additional load immediately prior to an overcurrent condition will not cause the switching node
voltage to exceed 20 V. Additionally, ensure during worst case operation, with all bucks loaded immediately prior
to current limit, the maximum virtual junction temperature of the device does not exceed 125°C.
All converters operate in hiccup mode: Once an over-current lasting more than 10 ms is sensed in any of the
converters, they will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has
been removed, the converter will ramp up and operate normally. If this is not the case the converter will see
another over-current event and shuts-down again repeating the cycle (hiccup) until the failure is cleared.
If an overload condition lasts for less than 10 ms, only the relevant converter affected will shut-down and re-start
and no global hiccup mode will occur.
Overvoltage Transient Protection
The device incorporates an overvoltage transient protection (OVP) circuit to minimize voltage overshoot. The
OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP
threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the FB voltage drops lower than the OVTP threshold which is 107%, the high side MOSFET is
allowed to turn on the next clock cycle.
Low Power/Pulse Skipping Operation
When a buck synchronous converter operates at light load or standby conditions, the switching losses are the
dominant source of power losses. Under these load conditions, TPS652510 uses a pulse skipping modulation
technique to reduce the switching losses by keeping the power transistors in the off-state for several switching
cycles, while maintaining a regulated output voltage. Figure 39 shows the output voltage and load plus the
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