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TPS652510 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
TPS652510 4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE DC-DC CONVERTERS WITH INTEGRATED FET TI
Texas Instruments TI
TPS652510 Datasheet PDF : 31 Pages
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TPS652510
SLVSB30B – SEPTEMBER 2011 – REVISED AUGUST 2013
www.ti.com
Delayed Start-Up
If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay
added is ~1.67 ms per nF connected to the pin. Note that the EN pins have a weak 1-Mpull-up to the 3V3 rail.
VIN
V7V
V3V
PB_in
De-bouncing
20mS
De-bouncing
20mS
INT
Internal EN
EN1
EN2
EN treshold
Enx rise time
dictated by CEN
200mS 1024 mS
EN3
All bucks are disabled
20-22 mS
Enable discharge
10-12mS
Pre-bias timing
4-5mS
Pre-biased output
Soft star rise time
dictated by C SS
BUCK1
BUCK2
BUCK3
Soft start timer
10ms watchdog
PG asserted
PGOOD
PG timer
100 ms
Figure 33. Delayed Start-Up
Out-of-Phase Operation
In order to reduce input ripple current, Buck1 and Buck2 operate 180° out-of-phase. This enables the system
having less input ripple, then to lower component cost, save board space and reduce EMI.
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1%
tolerance or better divider resistors. In order to improve efficiency at light load, start with a value close to 40 k
for the R1 resistor and use Equation 8 to calculate R2.
R2
=
R1×
æ
ç
è
0.8V
V
O
-
0.8V
ö
÷
ø
(8)
16
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