CXL5005P View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

View to exact match

CXL5005P

CMOS-CCD 1H Delay Line for NTSC with PLL

Sony Semiconductor 

Blook Diagram and Pin configuration

14

13

12

11

10

Auto-bias

circuit

Output & S/H

(1 BIT)

Clamp circuit

VCO

680 bit shift

register

φ1

φ2

Clock driver

9

8

Phase

comparator

1/3 counter

1

2

3

4

5

6

7

CXL5005M/P

Pin Description

Pin No. Symbol

1 VSS

2 VCL

3 VCOIN

4 VDD

5 PCOUT

6 NC

7 VCOOUT

8 VCL

9 CLK

10 NC

11 OUT

12 FEED

13 AUTO

14 IN

Description

GND

5V power supply

VCO input

9V power supply

Phase comparator output

VCO output

5V power supply

Clock input

Signal output

Feedback DC output

Autobias DC output

Signal input

Impedance [Ω]

> 100k

≈ 5k

≈ 5k

≈ 5k

600 to 1k

> 100k

≈ 10k

> 100k

–2–

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