CXL5005P View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

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CXL5005P

CMOS-CCD 1H Delay Line for NTSC with PLL

Sony Semiconductor 

CXL5005M/P

CMOS-CCD 1H Delay Line for NTSC with PLL

Description

The CXL5005M/P are general-purpose CCD delay

line ICs which provide 1H delay time of NTSC.

CXL5005M

14 pin SOP (Plastic)

CXL5005P

14 pin DIP (Plastic)

Features

• Low power consumption 90mW (Typ.)

• Small size package (14-pin SOP, DIP)

• Low differential gain DG = 3% (Typ.)

• Input signal ampiitude 180 IRE (= 1.28Vp-p, max.)

• Low input clock amplitude operation 200mVp-p (Min.)

• Built-in triple PLL circuit

• Built-in peripheral circuits (clock driver, timing

generator, auto-bias and output circuits)

Functions

• 680-bit CCD register

• Clock drivers

• Autobias circuit

• Sync tip clamp circuit

• Sample-and-hold circuit

• PLL (triple)

Structure

CMOS-CCD

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage

VDD

11

V

• Supply voltage

VCL

6

V

• Operating temperature

Topr –10 to +60 °C

• Storage temperature

Tstg –55 to +150 °C

• Allowable power dissipation PD

CXL5005M 400 mW

CXL5005P 800 mW

Recommended Operating Conditions

Supply voltage

VDD 9 ± 5%

V

VCL 5 ± 5%

V

Recommended Clock Conditions

• Input clock amplitude

VCLK 200mVp-p to 1.0Vp-p

(300mVp-p typ.)

• Clock frequency

fCLK 3.579545MHz

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–

E88Z40A79-PS

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