Z86E34 View Datasheet(PDF) - Zilog
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Z86E34 Datasheet PDF : 10 Pages
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PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
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Z86E33/733/E34
Z86E43/743/E44
1
CMOS Z8® OTP MICROCONTROLLERS
FEATURES
Device
ROM
(KBytes)
Z86E33
4
Z86733
8
Z86E34
16
Z86E43
4
Z86743
8
Z86E44
16
Note: *General-Purpose
RAM*
(Bytes)
237
237
237
236
236
236
I/O
Lines
24
24
24
32
32
32
Speed
(MHz)
16
16
16
16
16
16
s Standard Temperature (VCC = 3.5V to 5.5V)
s Extended Temperature (VCC = 4.5V to 5.5V)
s 28-Pin DIP/SOIC/PLCC Packages (E33/733/E34)
40-Pin DIP Package (E43/743/E44)
44-Pin PLCC/QFP Packages (E43/743/E44)
s Software Enabled Watch-Dog Timer (WDT)
s Push-Pull/Open-Drain Programmable on
Port 0, Port 1, and Port 2
s Low-Power Consumption: 60 mW
s Programmable Crystal Oscillator, EPROM Protect,
RAM Protect, Auto Latch Disable, Permanent WDT,
32 KHz Oscillator, and EPROM /Test Mode Disable
s Fast Instruction Pointer: 0.6µs
s Two Standby Modes: STOP and HALT
s 24/32 Input and Output Lines
s Digital Inputs CMOS Levels, Schmitt-Triggered
s Software Programmable Low EMI Mode
s Two Programmable 8-Bit Counter/Timers Each with a 6-
Bit Programmable Prescaler
s Six Vectored, Priority Interrupts from Six Different
Sources
s Auto Latches
s Auto Power-On Reset (POR)
s Two Comparators
s On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive
GENERAL DESCRIPTION
The Z86E33/733/E34/E43/743/E44 8-bit CMOS One-Time
Programmable (OTP) microcontrollers are members of
Zilog's Z8® single-chip microcontroller family featuring en-
hanced wake-up circuitry, programmable Watch-Dog Tim-
ers, Low Noise EMI options, and easy hardware/software
system expansion capability.
Four basic address spaces support a wide range of mem-
ory configurations. The designer has easy access to regis-
ter mapped peripheral and I/O circuits.
For applications demanding powerful I/O capabilities, the
Z86E33/733/E34 have 24 pins and the Z86E43/743/E44
have 32 pins of dedicated input and output. These lines are
grouped into four ports, eight lines per port, and are config-
urable under software control to provide timing, status sig-
nals, and parallel I/O with or without handshake, and ad-
dress/data bus for interfacing external memory.
Notes: All Signals with a preceding front slash, "/", are
active Low, e.g., B//W (WORD is active Low); /B/W (BYTE
is active Low, only).
CP97DZ83300
PRELIMINARY
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