Z86E4416FEC View Datasheet(PDF) - Zilog
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Z86E4416FEC Datasheet PDF : 10 Pages
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Zilog
ABSOLUTE MAXIMUM RATINGS
Z86E33/733/E34/E43/743/E44
CMOS Z8® OTP Microcontrollers
Parameter
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to VSS [Note 1]
Voltage on VDD Pin with Respect to VSS
Voltage on XTAL1 and /RESET Pins with Respect to VSS [Note 2]
Total Power Dissipation
Maximum Allowable Current out of VSS
Maximum Allowable Current into VDD
Maximum Allowable Current into an Input Pin [Note 3]
Maximum Allowable Current into an Open-Drain Pin [Note 4]
Maximum Allowable Output Current Sinked by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
Notes:
1. This applies to all pins except XTAL pins and where otherwise noted.
2. There is no input protection diode from pin to VDD.
3. This excludes XTAL pins.
4. Device pin is not at an output Low state.
Min
–40
–65
–0.6
–0.3
–0.6
–600
–600
Max
+105
+150
+7
+7
V DD+1
1.21
220
180
+600
+600
25
25
Units
1
C
C
V
V
V
W
mA
mA
µA
µA
mA
mA
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper-
ational sections of these specifications is not implied. Ex-
posure to absolute maximum rating conditions for an ex-
tended period may affect device reliability.
Total power dissipation should not exceed 1.2 W for the
package. Power dissipation is calculated as follows:
Total Power Dissipation = VDD x [ IDD – (sum of IOH) ]
+ sum of [ (VDD – VOH) x IOH ]
+ sum of (V0L x I0L)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Test Load).
From Output
Under Test
150 pF
Figure 7. Test Load Diagram
CP97DZ83300
PRELIMINARY
7
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