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TMP320C33FN150 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
TMP320C33FN150 DIGITAL SIGNAL PROCESSOR TI
Texas Instruments TI
TMP320C33FN150 Datasheet PDF : 57 Pages
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TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004
Terminal Functions
TERMINAL
TYPE†
NAME
QTY
DESCRIPTION
CONDITIONS
WHEN
SIGNAL IS Z TYPE‡
PRIMARY-BUS INTERFACE
D31 −D0
32-bit data port
32 I / O / Z
Data port bus keepers (See Figure 9)
S
H
R
S
A23 −A0
24
O / Z 24-bit address port
S
H
R
R/W
1
O/Z
Read / write. R/ W is high when a read is performed and low when a write is performed
over the parallel interface.
S
H
R
STRB
1
O / Z Strobe. For all external-accesses
S
H
PAGE0 −
PAGE3
1
O / Z Page strobes. Four decoded page strobes for external access.
S
H
R
RDY
1
I
Ready. RDY indicates that the external device is prepared for a transaction
completion.
HOLD
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23 −A0,
1
I
D31−D0, STRB, and R / W are placed in the high-impedance state and all
transactions over the primary-bus interface are held until HOLD becomes a logic high
or until the NOHOLD bit of the primary-bus-control register is set.
HOLDA
Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD.
1
O/Z
HOLDA indicates that A23−A0, D31−D0, STRB, and R / W are in the high-impedance
state and that all transactions over the bus are held. HOLDA is high in response to
S
a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
CONTROL SIGNALS
RESET
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
1
I becomes a logic high, execution begins from the location specified by the reset
vector.
EDGEMODE 1
I Edge mode. Enables interrupt edge mode detection.
INT3 −INT0
4
I External interrupts
IACK
1
O/Z
Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate when a section of code is being executed.
S
MCBL / MP
1
I Microcomputer Bootloader / microprocessor mode-select
SHZ
Shutdown high impedance. When active, SHZ places all pins in the high-impedance
1
I
state. SHZ can be used for board-level testing or to ensure that no dual-drive
conditions occur. CAUTION: A low on SHZ corrupts the device memory and register
contents. Reset the device with SHZ high to restore it to a known operating condition.
XF1, XF0
2
I/O/Z
External flags. XF1 and XF0 are used as general-purpose I / Os or to support
interlocked processor instruction.
S
R
SERIAL PORT 0 SIGNALS
CLKR0
1
I / O / Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S
R
CLKX0
1
I/O/Z
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter.
S
R
DR0
1
I / O / Z Data-receive. Serial port 0 receives serial data on DR0.
S
R
DX0
1
I / O / Z Data-transmit output. Serial port 0 transmits serial data on DX0.
S
R
FSR0
1
I/O/Z
Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0.
S
R
FSX0
1
I/O/Z
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0.
S
R
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
§ Recommended decoupling. Four 0.1 µF for CVDD and eight 0.1 µF for DVDD.
6
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