|TMP100MDBVREP||DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE|
|TMP100MDBVREP Datasheet PDF : 22 Pages |
DIGITAL TEMPERATURE SENSOR
WITH I2C INTERFACE
SGLS254A − JULY 2005 - REVISED APRIL 2010
fault queue (F1/F0)
A fault condition occurs when the measured temperature exceeds the limits set in the THIGH and TLOW registers.
Additionally, the number of fault conditions required to generate an alert may be programmed using the fault
queue. The fault queue is provided to prevent a false alert due to environmental noise and requires consecutive
fault measurements to trigger the alert function. Table 7 defines the number of measured faults that may be
programmed to trigger an alert condition.
Table 7. Fault Settings of the TMP100 and TMP101
converter resolution (R1/R0)
The converter resolution bits control the resolution of the internal analog-to-digital (A/D) converter. This allows
the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 8 identifies
the resolution bits and relationship between resolution and conversion time.
9 Bits (0.5°C)
10 Bits (0.25°C)
11 Bits (0.125°C)
12 Bits (0.0625°C)
Table 8. Resolution of the TMP100
The TMP100 and TMP101 feature a one-shot temperature measurement mode. When the device is in
shutdown mode, writing a 1 to the OS/ALERT bit starts a single temperature conversion. The device returns
to the shutdown state at the completion of the single conversion. This is useful to reduce power consumption
in the TMP100 and TMP101 when continuous monitoring of temperature is not required.
Reading the OS/ALERT bit provides information about the comparator mode status. The state of the POL bit
will invert the polarity of data returned from the OS/ALERT bit. For POL = 0, the OS/ALERT reads as 1 until the
temperature equals or exceeds THIGH for the programmed number of consecutive faults, causing the
OS/ALERT bit to read as 0. The OS/ALERT bit continues to read as 0 until the temperature falls below TLOW
for the programmed number of consecutive faults when it again reads as 1. The status of the TM bit does not
affect the status of the OS/ALERT bit.
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