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TMP100NA/3KG4 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
TMP100NA/3KG4 Digital Temperature Sensor with I²C™ Interface TI
Texas Instruments TI
TMP100NA/3KG4 Datasheet PDF : 19 Pages
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TMP100
TMP101
SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007
SERIAL BUS ADDRESS
To program the TMP100 and TMP101, the master must
first address slave devices via a slave address byte. The
slave address byte consists of seven address bits, and a
direction bit indicating the intent of executing a read or
write operation.
The TMP100 features two address pins to allow up to eight
devices to be addressed on a single I2C interface. Table 11
describes the pin logic levels used to properly connect up
to eight devices. Float indicates the pin is left unconnected.
The state of pins ADD0 and ADD1 is sampled on the first
I2C bus communication and should be set prior to any
activity on the interface.
Table 11. Address Pins and Slave Addresses for
the TMP100
ADD1
0
0
0
1
1
1
Float
Float
ADD0
0
Float
1
0
Float
1
0
1
SLAVE ADDRESS
1001000
1001001
1001010
1001100
1001101
1001110
1001011
1001111
The TMP101 features one address pin and an ALERT pin,
allowing up to three devices to be connected per bus. Pin
logic levels are described in Table 12. The address pins of
the TMP100 and TMP101 are read after reset or in
response to an I2C address acquire request. Following
reading, the state of the address pins is latched to
minimize power dissipation associated with detection.
Table 12. Address Pins and Slave Addresses for
the TMP101
ADD0
0
Float
1
SLAVE ADDRESS
1001000
1001001
1001010
BUS OVERVIEW
The device that initiates the transfer is called a master, and
the devices controlled by the master are slaves. The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions.
To address a specific device, a START condition is
initiated, indicated by pulling the data-line (SDA) from a
HIGH to LOW logic level while SCL is HIGH. All slaves on
the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended.
During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge
and pulling SDA LOW.
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Data transfer is then initiated and sent over eight clock
pulses followed by an Acknowledge Bit. During data
transfer SDA must remain stable while SCL is HIGH, as
any change in SDA while SCL is HIGH will be interpreted
as a control signal.
Once all data have been transferred, the master generates
a STOP condition indicated by pulling SDA from LOW to
HIGH, while SCL is HIGH.
WRITING/READING TO THE TMP100 AND
TMP101
Accessing a particular register on the TMP100 and
TMP101 is accomplished by writing the appropriate value
to the Pointer Register. The value for the Pointer Register
is the first byte transferred after the I2C slave address byte
with the R/W bit LOW. Every write operation to the
TMP100 and TMP101 requires a value for the Pointer
Register. (Refer to Figure 6.)
When reading from the TMP100 and TMP101, the last
value stored in the Pointer Register by a write operation is
used to determine which register is read by a read
operation. To change the register pointer for a read
operation, a new value must be written to the Pointer
Register. This is accomplished by issuing an I2C slave
address byte with the R/W bit LOW, followed by the Pointer
Register Byte. No additional data are required. The master
can then generate a START condition and send the I2C
slave address byte with the R/W bit HIGH to initiate the
read command. See Figure 7 for details of this sequence.
If repeated reads from the same register are desired, it is
not necessary to continually send the Pointer Register
bytes as the TMP100 and TMP101 will remember the
Pointer Register value until it is changed by the next write
operation.
SLAVE MODE OPERATIONS
The TMP100 and TMP101 can operate as slave receivers
or slave transmitters.
Slave Receiver Mode:
The first byte transmitted by the master is the slave
address, with the R/W bit LOW. The TMP100 or TMP101
then acknowledges reception of a valid address. The next
byte transmitted by the master is the Pointer Register. The
TMP100 or TMP101 then acknowledges reception of the
Pointer Register byte. The next byte or bytes are written to
the register addressed by the Pointer Register. The
TMP100 and TMP101 will acknowledge reception of each
data byte. The master may terminate data transfer by
generating a START or STOP condition.
Slave Transmitter Mode:
The first byte is transmitted by the master and is the slave
address, with the R/W bit HIGH. The slave acknowledges
reception of a valid slave address. The next byte is
transmitted by the slave and is the most significant byte of
the register indicated by the Pointer Register. The master
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